src/arch/arm/ArmSystem.py

   1 # Copyright (c) 2009, 2012-2013, 2015-2020 ARM Limited
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  35
  36 from m5.params import *
  37 from m5.options import *
  38 from m5.SimObject import *
  39 from m5.util.fdthelper import *
  40
  41 from m5.objects.System import System
  42 from m5.objects.ArmSemihosting import ArmSemihosting
  43
  44 class SveVectorLength(UInt8): min = 1; max = 16
  45
  46 class ArmSystem(System):
  47     type = 'ArmSystem'
  48     cxx_header = "arch/arm/system.hh"
  49     multi_proc = Param.Bool(True, "Multiprocessor system?")
  50     gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface")
  51     have_security = Param.Bool(False,
  52         "True if Security Extensions are implemented")
  53     have_virtualization = Param.Bool(False,
  54         "True if Virtualization Extensions are implemented")
  55     have_crypto = Param.Bool(False,
  56         "True if Crypto Extensions is implemented")
  57     have_lpae = Param.Bool(True, "True if LPAE is implemented")
  58     reset_addr = Param.Addr(0x0,
  59         "Reset address (ARMv8)")
  60     auto_reset_addr = Param.Bool(True,
  61         "Determine reset address from kernel entry point if no boot loader")
  62     highest_el_is_64 = Param.Bool(True,
  63         "True if the register width of the highest implemented exception level "
  64         "is 64 bits (ARMv8)")
  65     phys_addr_range_64 = Param.UInt8(40,
  66         "Supported physical address range in bits when using AArch64 (ARMv8)")
  67     have_large_asid_64 = Param.Bool(False,
  68         "True if ASID is 16 bits in AArch64 (ARMv8)")
  69     have_sve = Param.Bool(True,
  70         "True if SVE is implemented (ARMv8)")
  71     sve_vl = Param.SveVectorLength(1,
  72         "SVE vector length in quadwords (128-bit)")
  73     have_lse = Param.Bool(True,
  74         "True if LSE is implemented (ARMv8.1)")
  75     have_pan = Param.Bool(True,
  76         "True if Priviledge Access Never is implemented (ARMv8.1)")
  77     have_secel2 = Param.Bool(True,
  78         "True if Secure EL2 is implemented (ARMv8)")
  79     have_tme = Param.Bool(False,
  80         "True if transactional memory extension (TME) is implemented")
  81     semihosting = Param.ArmSemihosting(NULL,
  82         "Enable support for the Arm semihosting by settings this parameter")
  83
  84     # Set to true if simulation provides a PSCI implementation
  85     # This flag will be checked when auto-generating
  86     # a PSCI node. A client (e.g Linux) would then be able to
  87     # know if it can use the PSCI APIs
  88     _have_psci = False
  89
  90     def generateDtb(self, filename):
  91         """
  92         Autogenerate DTB. Arguments are the folder where the DTB
  93         will be stored, and the name of the DTB file.
  94         """
  95         state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
  96         rootNode = self.generateDeviceTree(state)
  97
  98         fdt = Fdt()
  99         fdt.add_rootnode(rootNode)
 100         fdt.writeDtbFile(filename)
 101
 102
 103     def generateDeviceTree(self, state):
 104         # Generate a device tree root node for the system by creating the root
 105         # node and adding the generated subnodes of all children.
 106         # When a child needs to add multiple nodes, this is done by also
 107         # creating a node called '/' which will then be merged with the
 108         # root instead of appended.
 109
 110         def generateMemNode(mem_range):
 111             node = FdtNode("memory@%x" % int(mem_range.start))
 112             node.append(FdtPropertyStrings("device_type", ["memory"]))
 113             node.append(FdtPropertyWords("reg",
 114                 state.addrCells(mem_range.start) +
 115                 state.sizeCells(mem_range.size()) ))
 116             return node
 117
 118         root = FdtNode('/')
 119         root.append(state.addrCellsProperty())
 120         root.append(state.sizeCellsProperty())
 121
 122         # Add memory nodes
 123         for mem_range in self.mem_ranges:
 124             root.append(generateMemNode(mem_range))
 125
 126         for node in self.recurseDeviceTree(state):
 127             # Merge root nodes instead of adding them (for children
 128             # that need to add multiple root level nodes)
 129             if node.get_name() == root.get_name():
 130                 root.merge(node)
 131             else:
 132                 root.append(node)
 133
 134         return root