1 # Copyright (c) 2009, 2012-2013, 2015-2018 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 from m5
.params
import *
40 from m5
.options
import *
41 from m5
.SimObject
import *
42 from m5
.util
.fdthelper
import *
44 from System
import System
45 from ArmSemihosting
import ArmSemihosting
47 class ArmMachineType(Enum
):
50 'VExpress_EMM' : 2272,
51 'VExpress_EMM64' : 2272,
55 class ArmSystem(System
):
57 cxx_header
= "arch/arm/system.hh"
58 multi_proc
= Param
.Bool(True, "Multiprocessor system?")
59 boot_loader
= VectorParam
.String([],
60 "File that contains the boot loader code. Zero or more files may be "
61 "specified. The first boot loader that matches the kernel's "
62 "architecture will be used.")
63 gic_cpu_addr
= Param
.Addr(0, "Addres of the GIC CPU interface")
64 flags_addr
= Param
.Addr(0, "Address of the flags register for MP booting")
65 have_security
= Param
.Bool(False,
66 "True if Security Extensions are implemented")
67 have_virtualization
= Param
.Bool(False,
68 "True if Virtualization Extensions are implemented")
69 have_crypto
= Param
.Bool(False,
70 "True if Crypto Extensions is implemented")
71 have_lpae
= Param
.Bool(True, "True if LPAE is implemented")
72 reset_addr
= Param
.Addr(0x0,
73 "Reset address (ARMv8)")
74 auto_reset_addr
= Param
.Bool(False,
75 "Determine reset address from kernel entry point if no boot loader")
76 highest_el_is_64
= Param
.Bool(False,
77 "True if the register width of the highest implemented exception level "
79 phys_addr_range_64
= Param
.UInt8(40,
80 "Supported physical address range in bits when using AArch64 (ARMv8)")
81 have_large_asid_64
= Param
.Bool(False,
82 "True if ASID is 16 bits in AArch64 (ARMv8)")
84 semihosting
= Param
.ArmSemihosting(NULL
,
85 "Enable support for the Arm semihosting by settings this parameter")
87 m5ops_base
= Param
.Addr(0,
88 "Base of the 64KiB PA range used for memory-mapped m5ops. Set to 0 "
91 def generateDeviceTree(self
, state
):
92 # Generate a device tree root node for the system by creating the root
93 # node and adding the generated subnodes of all children.
94 # When a child needs to add multiple nodes, this is done by also
95 # creating a node called '/' which will then be merged with the
96 # root instead of appended.
98 def generateMemNode(mem_range
):
99 node
= FdtNode("memory@%x" % long(mem_range
.start
))
100 node
.append(FdtPropertyStrings("device_type", ["memory"]))
101 node
.append(FdtPropertyWords("reg",
102 state
.addrCells(mem_range
.start
) +
103 state
.sizeCells(mem_range
.size()) ))
107 root
.append(state
.addrCellsProperty())
108 root
.append(state
.sizeCellsProperty())
111 for mem_range
in self
.mem_ranges
:
112 root
.append(generateMemNode(mem_range
))
114 for node
in self
.recurseDeviceTree(state
):
115 # Merge root nodes instead of adding them (for children
116 # that need to add multiple root level nodes)
117 if node
.get_name() == root
.get_name():
124 class GenericArmSystem(ArmSystem
):
125 type = 'GenericArmSystem'
126 cxx_header
= "arch/arm/system.hh"
127 machine_type
= Param
.ArmMachineType('DTOnly',
128 "Machine id from http://www.arm.linux.org.uk/developer/machines/")
129 atags_addr
= Param
.Addr("Address where default atags structure should " \
131 dtb_filename
= Param
.String("",
132 "File that contains the Device Tree Blob. Don't use DTB if empty.")
133 early_kernel_symbols
= Param
.Bool(False,
134 "enable early kernel symbol tables before MMU")
135 enable_context_switch_stats_dump
= Param
.Bool(False, "enable stats/task info dumping at context switch boundaries")
137 panic_on_panic
= Param
.Bool(False, "Trigger a gem5 panic if the " \
138 "guest kernel panics")
139 panic_on_oops
= Param
.Bool(False, "Trigger a gem5 panic if the " \
140 "guest kernel oopses")
142 def generateDtb(self
, outdir
, filename
):
144 Autogenerate DTB. Arguments are the folder where the DTB
145 will be stored, and the name of the DTB file.
147 state
= FdtState(addr_cells
=2, size_cells
=2, cpu_cells
=1)
148 rootNode
= self
.generateDeviceTree(state
)
151 fdt
.add_rootnode(rootNode
)
152 dtb_filename
= os
.path
.join(outdir
, filename
)
153 self
.dtb_filename
= fdt
.writeDtbFile(dtb_filename
)
155 class LinuxArmSystem(GenericArmSystem
):
156 type = 'LinuxArmSystem'
157 cxx_header
= "arch/arm/linux/system.hh"
161 """Dump dmesg from the simulated kernel to standard out"""
164 # Have Linux systems for ARM auto-calc their load_addr_mask for proper
168 class FreebsdArmSystem(GenericArmSystem
):
169 type = 'FreebsdArmSystem'
170 cxx_header
= "arch/arm/freebsd/system.hh"