1 # Copyright (c) 2009, 2012-2013, 2015-2017 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 from m5
.params
import *
40 from m5
.SimObject
import *
41 from m5
.util
.fdthelper
import *
43 from System
import System
45 class ArmMachineType(Enum
):
49 'VExpress_EMM' : 2272,
50 'VExpress_EMM64' : 2272,
54 class ArmSystem(System
):
56 cxx_header
= "arch/arm/system.hh"
57 multi_proc
= Param
.Bool(True, "Multiprocessor system?")
58 boot_loader
= VectorParam
.String([],
59 "File that contains the boot loader code. Zero or more files may be "
60 "specified. The first boot loader that matches the kernel's "
61 "architecture will be used.")
62 gic_cpu_addr
= Param
.Addr(0, "Addres of the GIC CPU interface")
63 flags_addr
= Param
.Addr(0, "Address of the flags register for MP booting")
64 have_security
= Param
.Bool(False,
65 "True if Security Extensions are implemented")
66 have_virtualization
= Param
.Bool(False,
67 "True if Virtualization Extensions are implemented")
68 have_lpae
= Param
.Bool(True, "True if LPAE is implemented")
69 highest_el_is_64
= Param
.Bool(False,
70 "True if the register width of the highest implemented exception level "
72 reset_addr_64
= Param
.Addr(0x0,
73 "Reset address if the highest implemented exception level is 64 bits "
75 phys_addr_range_64
= Param
.UInt8(40,
76 "Supported physical address range in bits when using AArch64 (ARMv8)")
77 have_large_asid_64
= Param
.Bool(False,
78 "True if ASID is 16 bits in AArch64 (ARMv8)")
80 m5ops_base
= Param
.Addr(0,
81 "Base of the 64KiB PA range used for memory-mapped m5ops. Set to 0 "
84 def generateDeviceTree(self
, state
):
85 # Generate a device tree root node for the system by creating the root
86 # node and adding the generated subnodes of all children.
87 # When a child needs to add multiple nodes, this is done by also
88 # creating a node called '/' which will then be merged with the
89 # root instead of appended.
91 def generateMemNode(mem_range
):
92 node
= FdtNode("memory@%x" % long(mem_range
.start
))
93 node
.append(FdtPropertyStrings("device_type", ["memory"]))
94 node
.append(FdtPropertyWords("reg",
95 state
.addrCells(mem_range
.start
) +
96 state
.sizeCells(mem_range
.size()) ))
100 root
.append(state
.addrCellsProperty())
101 root
.append(state
.sizeCellsProperty())
104 for mem_range
in self
.mem_ranges
:
105 root
.append(generateMemNode(mem_range
))
107 for node
in self
.recurseDeviceTree(state
):
108 # Merge root nodes instead of adding them (for children
109 # that need to add multiple root level nodes)
110 if node
.get_name() == root
.get_name():
117 class GenericArmSystem(ArmSystem
):
118 type = 'GenericArmSystem'
119 cxx_header
= "arch/arm/system.hh"
120 machine_type
= Param
.ArmMachineType('DTOnly',
121 "Machine id from http://www.arm.linux.org.uk/developer/machines/")
122 atags_addr
= Param
.Addr("Address where default atags structure should " \
124 dtb_filename
= Param
.String("",
125 "File that contains the Device Tree Blob. Don't use DTB if empty.")
126 early_kernel_symbols
= Param
.Bool(False,
127 "enable early kernel symbol tables before MMU")
128 enable_context_switch_stats_dump
= Param
.Bool(False, "enable stats/task info dumping at context switch boundaries")
130 panic_on_panic
= Param
.Bool(False, "Trigger a gem5 panic if the " \
131 "guest kernel panics")
132 panic_on_oops
= Param
.Bool(False, "Trigger a gem5 panic if the " \
133 "guest kernel oopses")
135 class LinuxArmSystem(GenericArmSystem
):
136 type = 'LinuxArmSystem'
137 cxx_header
= "arch/arm/linux/system.hh"
141 """Dump dmesg from the simulated kernel to standard out"""
144 # Have Linux systems for ARM auto-calc their load_addr_mask for proper
148 class FreebsdArmSystem(GenericArmSystem
):
149 type = 'FreebsdArmSystem'
150 cxx_header
= "arch/arm/freebsd/system.hh"