arm: Delete authors lists from the arm files.
[gem5.git] / src / arch / arm / ArmSystem.py
1 # Copyright (c) 2009, 2012-2013, 2015-2019 ARM Limited
2 # All rights reserved.
3 #
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35
36 from m5.params import *
37 from m5.options import *
38 from m5.SimObject import *
39 from m5.util.fdthelper import *
40
41 from m5.objects.System import System
42 from m5.objects.ArmSemihosting import ArmSemihosting
43
44 class ArmMachineType(Enum):
45 map = {
46 'VExpress_EMM' : 2272,
47 'VExpress_EMM64' : 2272,
48 'DTOnly' : -1,
49 }
50
51 class SveVectorLength(UInt8): min = 1; max = 16
52
53 class ArmSystem(System):
54 type = 'ArmSystem'
55 cxx_header = "arch/arm/system.hh"
56 multi_proc = Param.Bool(True, "Multiprocessor system?")
57 boot_loader = VectorParam.String([],
58 "File that contains the boot loader code. Zero or more files may be "
59 "specified. The first boot loader that matches the kernel's "
60 "architecture will be used.")
61 gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface")
62 flags_addr = Param.Addr(0, "Address of the flags register for MP booting")
63 have_security = Param.Bool(False,
64 "True if Security Extensions are implemented")
65 have_virtualization = Param.Bool(False,
66 "True if Virtualization Extensions are implemented")
67 have_crypto = Param.Bool(False,
68 "True if Crypto Extensions is implemented")
69 have_lpae = Param.Bool(True, "True if LPAE is implemented")
70 reset_addr = Param.Addr(0x0,
71 "Reset address (ARMv8)")
72 auto_reset_addr = Param.Bool(False,
73 "Determine reset address from kernel entry point if no boot loader")
74 highest_el_is_64 = Param.Bool(False,
75 "True if the register width of the highest implemented exception level "
76 "is 64 bits (ARMv8)")
77 phys_addr_range_64 = Param.UInt8(40,
78 "Supported physical address range in bits when using AArch64 (ARMv8)")
79 have_large_asid_64 = Param.Bool(False,
80 "True if ASID is 16 bits in AArch64 (ARMv8)")
81 have_sve = Param.Bool(True,
82 "True if SVE is implemented (ARMv8)")
83 sve_vl = Param.SveVectorLength(1,
84 "SVE vector length in quadwords (128-bit)")
85 have_lse = Param.Bool(True,
86 "True if LSE is implemented (ARMv8.1)")
87 have_pan = Param.Bool(True,
88 "True if Priviledge Access Never is implemented (ARMv8.1)")
89
90 semihosting = Param.ArmSemihosting(NULL,
91 "Enable support for the Arm semihosting by settings this parameter")
92
93 dtb_filename = Param.String("",
94 "File that contains the Device Tree Blob. Don't use DTB if empty.")
95
96 def generateDtb(self, outdir, filename):
97 """
98 Autogenerate DTB. Arguments are the folder where the DTB
99 will be stored, and the name of the DTB file.
100 """
101 state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
102 rootNode = self.generateDeviceTree(state)
103
104 fdt = Fdt()
105 fdt.add_rootnode(rootNode)
106 dtb_filename = os.path.join(outdir, filename)
107 self.dtb_filename = fdt.writeDtbFile(dtb_filename)
108
109
110 def generateDeviceTree(self, state):
111 # Generate a device tree root node for the system by creating the root
112 # node and adding the generated subnodes of all children.
113 # When a child needs to add multiple nodes, this is done by also
114 # creating a node called '/' which will then be merged with the
115 # root instead of appended.
116
117 def generateMemNode(mem_range):
118 node = FdtNode("memory@%x" % long(mem_range.start))
119 node.append(FdtPropertyStrings("device_type", ["memory"]))
120 node.append(FdtPropertyWords("reg",
121 state.addrCells(mem_range.start) +
122 state.sizeCells(mem_range.size()) ))
123 return node
124
125 root = FdtNode('/')
126 root.append(state.addrCellsProperty())
127 root.append(state.sizeCellsProperty())
128
129 # Add memory nodes
130 for mem_range in self.mem_ranges:
131 root.append(generateMemNode(mem_range))
132
133 for node in self.recurseDeviceTree(state):
134 # Merge root nodes instead of adding them (for children
135 # that need to add multiple root level nodes)
136 if node.get_name() == root.get_name():
137 root.merge(node)
138 else:
139 root.append(node)
140
141 return root
142
143 class GenericArmSystem(ArmSystem):
144 type = 'GenericArmSystem'
145 cxx_header = "arch/arm/system.hh"
146 machine_type = Param.ArmMachineType('DTOnly',
147 "Machine id from http://www.arm.linux.org.uk/developer/machines/")
148 atags_addr = Param.Addr("Address where default atags structure should " \
149 "be written")
150 early_kernel_symbols = Param.Bool(False,
151 "enable early kernel symbol tables before MMU")
152 enable_context_switch_stats_dump = Param.Bool(False,
153 "enable stats/task info dumping at context switch boundaries")
154
155 panic_on_panic = Param.Bool(False, "Trigger a gem5 panic if the " \
156 "guest kernel panics")
157 panic_on_oops = Param.Bool(False, "Trigger a gem5 panic if the " \
158 "guest kernel oopses")
159
160 class LinuxArmSystem(GenericArmSystem):
161 type = 'LinuxArmSystem'
162 cxx_header = "arch/arm/linux/system.hh"
163
164 @cxxMethod
165 def dumpDmesg(self):
166 """Dump dmesg from the simulated kernel to standard out"""
167 pass
168
169 # Have Linux systems for ARM auto-calc their load_addr_mask for proper
170 # kernel relocation.
171 load_addr_mask = 0x0
172
173 class FreebsdArmSystem(GenericArmSystem):
174 type = 'FreebsdArmSystem'
175 cxx_header = "arch/arm/freebsd/system.hh"