1 # Copyright (c) 2009, 2012-2013, 2015-2019 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 from m5
.params
import *
37 from m5
.options
import *
38 from m5
.SimObject
import *
39 from m5
.util
.fdthelper
import *
41 from m5
.objects
.System
import System
42 from m5
.objects
.ArmSemihosting
import ArmSemihosting
44 class ArmMachineType(Enum
):
46 'VExpress_EMM' : 2272,
47 'VExpress_EMM64' : 2272,
51 class SveVectorLength(UInt8
): min = 1; max = 16
53 class ArmSystem(System
):
55 cxx_header
= "arch/arm/system.hh"
56 multi_proc
= Param
.Bool(True, "Multiprocessor system?")
57 boot_loader
= VectorParam
.String([],
58 "File that contains the boot loader code. Zero or more files may be "
59 "specified. The first boot loader that matches the kernel's "
60 "architecture will be used.")
61 gic_cpu_addr
= Param
.Addr(0, "Addres of the GIC CPU interface")
62 flags_addr
= Param
.Addr(0, "Address of the flags register for MP booting")
63 have_security
= Param
.Bool(False,
64 "True if Security Extensions are implemented")
65 have_virtualization
= Param
.Bool(False,
66 "True if Virtualization Extensions are implemented")
67 have_crypto
= Param
.Bool(False,
68 "True if Crypto Extensions is implemented")
69 have_lpae
= Param
.Bool(True, "True if LPAE is implemented")
70 reset_addr
= Param
.Addr(0x0,
71 "Reset address (ARMv8)")
72 auto_reset_addr
= Param
.Bool(False,
73 "Determine reset address from kernel entry point if no boot loader")
74 highest_el_is_64
= Param
.Bool(False,
75 "True if the register width of the highest implemented exception level "
77 phys_addr_range_64
= Param
.UInt8(40,
78 "Supported physical address range in bits when using AArch64 (ARMv8)")
79 have_large_asid_64
= Param
.Bool(False,
80 "True if ASID is 16 bits in AArch64 (ARMv8)")
81 have_sve
= Param
.Bool(True,
82 "True if SVE is implemented (ARMv8)")
83 sve_vl
= Param
.SveVectorLength(1,
84 "SVE vector length in quadwords (128-bit)")
85 have_lse
= Param
.Bool(True,
86 "True if LSE is implemented (ARMv8.1)")
87 have_pan
= Param
.Bool(True,
88 "True if Priviledge Access Never is implemented (ARMv8.1)")
90 semihosting
= Param
.ArmSemihosting(NULL
,
91 "Enable support for the Arm semihosting by settings this parameter")
93 dtb_filename
= Param
.String("",
94 "File that contains the Device Tree Blob. Don't use DTB if empty.")
96 def generateDtb(self
, outdir
, filename
):
98 Autogenerate DTB. Arguments are the folder where the DTB
99 will be stored, and the name of the DTB file.
101 state
= FdtState(addr_cells
=2, size_cells
=2, cpu_cells
=1)
102 rootNode
= self
.generateDeviceTree(state
)
105 fdt
.add_rootnode(rootNode
)
106 dtb_filename
= os
.path
.join(outdir
, filename
)
107 self
.dtb_filename
= fdt
.writeDtbFile(dtb_filename
)
110 def generateDeviceTree(self
, state
):
111 # Generate a device tree root node for the system by creating the root
112 # node and adding the generated subnodes of all children.
113 # When a child needs to add multiple nodes, this is done by also
114 # creating a node called '/' which will then be merged with the
115 # root instead of appended.
117 def generateMemNode(mem_range
):
118 node
= FdtNode("memory@%x" % long(mem_range
.start
))
119 node
.append(FdtPropertyStrings("device_type", ["memory"]))
120 node
.append(FdtPropertyWords("reg",
121 state
.addrCells(mem_range
.start
) +
122 state
.sizeCells(mem_range
.size()) ))
126 root
.append(state
.addrCellsProperty())
127 root
.append(state
.sizeCellsProperty())
130 for mem_range
in self
.mem_ranges
:
131 root
.append(generateMemNode(mem_range
))
133 for node
in self
.recurseDeviceTree(state
):
134 # Merge root nodes instead of adding them (for children
135 # that need to add multiple root level nodes)
136 if node
.get_name() == root
.get_name():
143 class GenericArmSystem(ArmSystem
):
144 type = 'GenericArmSystem'
145 cxx_header
= "arch/arm/system.hh"
146 machine_type
= Param
.ArmMachineType('DTOnly',
147 "Machine id from http://www.arm.linux.org.uk/developer/machines/")
148 atags_addr
= Param
.Addr("Address where default atags structure should " \
150 early_kernel_symbols
= Param
.Bool(False,
151 "enable early kernel symbol tables before MMU")
152 enable_context_switch_stats_dump
= Param
.Bool(False,
153 "enable stats/task info dumping at context switch boundaries")
155 panic_on_panic
= Param
.Bool(False, "Trigger a gem5 panic if the " \
156 "guest kernel panics")
157 panic_on_oops
= Param
.Bool(False, "Trigger a gem5 panic if the " \
158 "guest kernel oopses")
160 class LinuxArmSystem(GenericArmSystem
):
161 type = 'LinuxArmSystem'
162 cxx_header
= "arch/arm/linux/system.hh"
166 """Dump dmesg from the simulated kernel to standard out"""
169 # Have Linux systems for ARM auto-calc their load_addr_mask for proper
173 class FreebsdArmSystem(GenericArmSystem
):
174 type = 'FreebsdArmSystem'
175 cxx_header
= "arch/arm/freebsd/system.hh"