src/arch/arm/ArmSystem.py

   1 # Copyright (c) 2009, 2012-2013, 2015-2019 ARM Limited
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  25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 #
  36 # Authors: Ali Saidi
  37 #          Glenn Bergmans
  38
  39 from m5.params import *
  40 from m5.options import *
  41 from m5.SimObject import *
  42 from m5.util.fdthelper import *
  43
  44 from m5.objects.System import System
  45 from m5.objects.ArmSemihosting import ArmSemihosting
  46
  47 class ArmMachineType(Enum):
  48     map = {
  49         'VExpress_EMM' : 2272,
  50         'VExpress_EMM64' : 2272,
  51         'DTOnly' : -1,
  52     }
  53
  54 class SveVectorLength(UInt8): min = 1; max = 16
  55
  56 class ArmSystem(System):
  57     type = 'ArmSystem'
  58     cxx_header = "arch/arm/system.hh"
  59     multi_proc = Param.Bool(True, "Multiprocessor system?")
  60     boot_loader = VectorParam.String([],
  61         "File that contains the boot loader code. Zero or more files may be "
  62         "specified. The first boot loader that matches the kernel's "
  63         "architecture will be used.")
  64     gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface")
  65     flags_addr = Param.Addr(0, "Address of the flags register for MP booting")
  66     have_security = Param.Bool(False,
  67         "True if Security Extensions are implemented")
  68     have_virtualization = Param.Bool(False,
  69         "True if Virtualization Extensions are implemented")
  70     have_crypto = Param.Bool(False,
  71         "True if Crypto Extensions is implemented")
  72     have_lpae = Param.Bool(True, "True if LPAE is implemented")
  73     reset_addr = Param.Addr(0x0,
  74         "Reset address (ARMv8)")
  75     auto_reset_addr = Param.Bool(False,
  76         "Determine reset address from kernel entry point if no boot loader")
  77     highest_el_is_64 = Param.Bool(False,
  78         "True if the register width of the highest implemented exception level "
  79         "is 64 bits (ARMv8)")
  80     phys_addr_range_64 = Param.UInt8(40,
  81         "Supported physical address range in bits when using AArch64 (ARMv8)")
  82     have_large_asid_64 = Param.Bool(False,
  83         "True if ASID is 16 bits in AArch64 (ARMv8)")
  84     have_sve = Param.Bool(True,
  85         "True if SVE is implemented (ARMv8)")
  86     sve_vl = Param.SveVectorLength(1,
  87         "SVE vector length in quadwords (128-bit)")
  88     have_lse = Param.Bool(True,
  89         "True if LSE is implemented (ARMv8.1)")
  90     have_pan = Param.Bool(True,
  91         "True if Priviledge Access Never is implemented (ARMv8.1)")
  92
  93     semihosting = Param.ArmSemihosting(NULL,
  94         "Enable support for the Arm semihosting by settings this parameter")
  95
  96     m5ops_base = Param.Addr(0,
  97         "Base of the 64KiB PA range used for memory-mapped m5ops. Set to 0 "
  98         "to disable.")
  99
 100     def generateDeviceTree(self, state):
 101         # Generate a device tree root node for the system by creating the root
 102         # node and adding the generated subnodes of all children.
 103         # When a child needs to add multiple nodes, this is done by also
 104         # creating a node called '/' which will then be merged with the
 105         # root instead of appended.
 106
 107         def generateMemNode(mem_range):
 108             node = FdtNode("memory@%x" % long(mem_range.start))
 109             node.append(FdtPropertyStrings("device_type", ["memory"]))
 110             node.append(FdtPropertyWords("reg",
 111                 state.addrCells(mem_range.start) +
 112                 state.sizeCells(mem_range.size()) ))
 113             return node
 114
 115         root = FdtNode('/')
 116         root.append(state.addrCellsProperty())
 117         root.append(state.sizeCellsProperty())
 118
 119         # Add memory nodes
 120         for mem_range in self.mem_ranges:
 121             root.append(generateMemNode(mem_range))
 122
 123         for node in self.recurseDeviceTree(state):
 124             # Merge root nodes instead of adding them (for children
 125             # that need to add multiple root level nodes)
 126             if node.get_name() == root.get_name():
 127                 root.merge(node)
 128             else:
 129                 root.append(node)
 130
 131         return root
 132
 133 class GenericArmSystem(ArmSystem):
 134     type = 'GenericArmSystem'
 135     cxx_header = "arch/arm/system.hh"
 136     machine_type = Param.ArmMachineType('DTOnly',
 137         "Machine id from http://www.arm.linux.org.uk/developer/machines/")
 138     atags_addr = Param.Addr("Address where default atags structure should " \
 139                                 "be written")
 140     dtb_filename = Param.String("",
 141         "File that contains the Device Tree Blob. Don't use DTB if empty.")
 142     early_kernel_symbols = Param.Bool(False,
 143         "enable early kernel symbol tables before MMU")
 144     enable_context_switch_stats_dump = Param.Bool(False, "enable stats/task info dumping at context switch boundaries")
 145
 146     panic_on_panic = Param.Bool(False, "Trigger a gem5 panic if the " \
 147                                     "guest kernel panics")
 148     panic_on_oops = Param.Bool(False, "Trigger a gem5 panic if the " \
 149                                    "guest kernel oopses")
 150
 151     def generateDtb(self, outdir, filename):
 152         """
 153         Autogenerate DTB. Arguments are the folder where the DTB
 154         will be stored, and the name of the DTB file.
 155         """
 156         state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
 157         rootNode = self.generateDeviceTree(state)
 158
 159         fdt = Fdt()
 160         fdt.add_rootnode(rootNode)
 161         dtb_filename = os.path.join(outdir, filename)
 162         self.dtb_filename = fdt.writeDtbFile(dtb_filename)
 163
 164 class LinuxArmSystem(GenericArmSystem):
 165     type = 'LinuxArmSystem'
 166     cxx_header = "arch/arm/linux/system.hh"
 167
 168     @cxxMethod
 169     def dumpDmesg(self):
 170         """Dump dmesg from the simulated kernel to standard out"""
 171         pass
 172
 173     # Have Linux systems for ARM auto-calc their load_addr_mask for proper
 174     # kernel relocation.
 175     load_addr_mask = 0x0
 176
 177 class FreebsdArmSystem(GenericArmSystem):
 178     type = 'FreebsdArmSystem'
 179     cxx_header = "arch/arm/freebsd/system.hh"