src/arch/arm/ArmTLB.py

   1 # -*- mode:python -*-
   2
   3 # Copyright (c) 2009, 2013 ARM Limited
   4 # All rights reserved.
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   9 # to a hardware implementation of the functionality of the software
  10 # licensed hereunder.  You may use the software subject to the license
  11 # terms below provided that you ensure that this notice is replicated
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  16 # modification, are permitted provided that the following conditions are
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  27 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  37 #
  38 # Authors: Ali Saidi
  39
  40 from m5.SimObject import SimObject
  41 from m5.params import *
  42 from m5.proxy import *
  43 from MemObject import MemObject
  44
  45 # Basic stage 1 translation objects
  46 class ArmTableWalker(MemObject):
  47     type = 'ArmTableWalker'
  48     cxx_class = 'ArmISA::TableWalker'
  49     cxx_header = "arch/arm/table_walker.hh"
  50     is_stage2 =  Param.Bool(False, "Is this object for stage 2 translation?")
  51     port = MasterPort("Port for TableWalker to do walk the translation with")
  52     sys = Param.System(Parent.any, "system object parameter")
  53     num_squash_per_cycle = Param.Unsigned(2,
  54             "Number of outstanding walks that can be squashed per cycle")
  55
  56 class ArmTLB(SimObject):
  57     type = 'ArmTLB'
  58     cxx_class = 'ArmISA::TLB'
  59     cxx_header = "arch/arm/tlb.hh"
  60     size = Param.Int(64, "TLB size")
  61     walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
  62     is_stage2 = Param.Bool(False, "Is this a stage 2 TLB?")
  63
  64 # Stage 2 translation objects, only used when virtualisation is being used
  65 class ArmStage2TableWalker(ArmTableWalker):
  66     is_stage2 = True
  67
  68 class ArmStage2TLB(ArmTLB):
  69     size = 32
  70     walker = ArmStage2TableWalker()
  71     is_stage2 = True
  72
  73 class ArmStage2MMU(SimObject):
  74     type = 'ArmStage2MMU'
  75     cxx_class = 'ArmISA::Stage2MMU'
  76     cxx_header = 'arch/arm/stage2_mmu.hh'
  77     tlb = Param.ArmTLB("Stage 1 TLB")
  78     stage2_tlb = Param.ArmTLB("Stage 2 TLB")
  79
  80 class ArmStage2IMMU(ArmStage2MMU):
  81     tlb = Parent.itb
  82     stage2_tlb = ArmStage2TLB(walker = ArmStage2TableWalker())
  83
  84 class ArmStage2DMMU(ArmStage2MMU):
  85     tlb = Parent.dtb
  86     stage2_tlb = ArmStage2TLB(walker = ArmStage2TableWalker())