src/arch/arm/ArmTLB.py

   1 # -*- mode:python -*-
   2
   3 # Copyright (c) 2009, 2013, 2015 ARM Limited
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  10 # licensed hereunder.  You may use the software subject to the license
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  37 #
  38 # Authors: Ali Saidi
  39
  40 from m5.SimObject import SimObject
  41 from m5.params import *
  42 from m5.proxy import *
  43 from m5.objects.BaseTLB import BaseTLB
  44 from m5.objects.ClockedObject import ClockedObject
  45
  46 # Basic stage 1 translation objects
  47 class ArmTableWalker(ClockedObject):
  48     type = 'ArmTableWalker'
  49     cxx_class = 'ArmISA::TableWalker'
  50     cxx_header = "arch/arm/table_walker.hh"
  51     is_stage2 =  Param.Bool(False, "Is this object for stage 2 translation?")
  52     num_squash_per_cycle = Param.Unsigned(2,
  53             "Number of outstanding walks that can be squashed per cycle")
  54
  55     # The port to the memory system. This port is ultimately belonging
  56     # to the Stage2MMU, and shared by the two table walkers, but we
  57     # access it through the ITB and DTB walked objects in the CPU for
  58     # symmetry with the other ISAs.
  59     port = MasterPort("Port used by the two table walkers")
  60
  61     sys = Param.System(Parent.any, "system object parameter")
  62
  63 class ArmTLB(BaseTLB):
  64     type = 'ArmTLB'
  65     cxx_class = 'ArmISA::TLB'
  66     cxx_header = "arch/arm/tlb.hh"
  67     sys = Param.System(Parent.any, "system object parameter")
  68     size = Param.Int(64, "TLB size")
  69     walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
  70     is_stage2 = Param.Bool(False, "Is this a stage 2 TLB?")
  71
  72 # Stage 2 translation objects, only used when virtualisation is being used
  73 class ArmStage2TableWalker(ArmTableWalker):
  74     is_stage2 = True
  75
  76 class ArmStage2TLB(ArmTLB):
  77     size = 32
  78     walker = ArmStage2TableWalker()
  79     is_stage2 = True
  80
  81 class ArmStage2MMU(SimObject):
  82     type = 'ArmStage2MMU'
  83     cxx_class = 'ArmISA::Stage2MMU'
  84     cxx_header = 'arch/arm/stage2_mmu.hh'
  85     tlb = Param.ArmTLB("Stage 1 TLB")
  86     stage2_tlb = Param.ArmTLB("Stage 2 TLB")
  87
  88     sys = Param.System(Parent.any, "system object parameter")
  89
  90 class ArmStage2IMMU(ArmStage2MMU):
  91     # We rely on the itb being a parameter of the CPU, and get the
  92     # appropriate object that way
  93     tlb = Parent.itb
  94     stage2_tlb = ArmStage2TLB()
  95
  96 class ArmStage2DMMU(ArmStage2MMU):
  97     # We rely on the dtb being a parameter of the CPU, and get the
  98     # appropriate object that way
  99     tlb = Parent.dtb
 100     stage2_tlb = ArmStage2TLB()