src/arch/arm/ArmTLB.py

   1 # -*- mode:python -*-
   2
   3 # Copyright (c) 2009, 2013, 2015 ARM Limited
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  37
  38 from m5.SimObject import SimObject
  39 from m5.params import *
  40 from m5.proxy import *
  41 from m5.objects.BaseTLB import BaseTLB
  42 from m5.objects.ClockedObject import ClockedObject
  43
  44 # Basic stage 1 translation objects
  45 class ArmTableWalker(ClockedObject):
  46     type = 'ArmTableWalker'
  47     cxx_class = 'ArmISA::TableWalker'
  48     cxx_header = "arch/arm/table_walker.hh"
  49     is_stage2 =  Param.Bool(False, "Is this object for stage 2 translation?")
  50     num_squash_per_cycle = Param.Unsigned(2,
  51             "Number of outstanding walks that can be squashed per cycle")
  52
  53     # The port to the memory system. This port is ultimately belonging
  54     # to the Stage2MMU, and shared by the two table walkers, but we
  55     # access it through the ITB and DTB walked objects in the CPU for
  56     # symmetry with the other ISAs.
  57     port = MasterPort("Port used by the two table walkers")
  58
  59     sys = Param.System(Parent.any, "system object parameter")
  60
  61 class ArmTLB(BaseTLB):
  62     type = 'ArmTLB'
  63     cxx_class = 'ArmISA::TLB'
  64     cxx_header = "arch/arm/tlb.hh"
  65     sys = Param.System(Parent.any, "system object parameter")
  66     size = Param.Int(64, "TLB size")
  67     walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
  68     is_stage2 = Param.Bool(False, "Is this a stage 2 TLB?")
  69
  70 # Stage 2 translation objects, only used when virtualisation is being used
  71 class ArmStage2TableWalker(ArmTableWalker):
  72     is_stage2 = True
  73
  74 class ArmStage2TLB(ArmTLB):
  75     size = 32
  76     walker = ArmStage2TableWalker()
  77     is_stage2 = True
  78
  79 class ArmStage2MMU(SimObject):
  80     type = 'ArmStage2MMU'
  81     cxx_class = 'ArmISA::Stage2MMU'
  82     cxx_header = 'arch/arm/stage2_mmu.hh'
  83     tlb = Param.ArmTLB("Stage 1 TLB")
  84     stage2_tlb = Param.ArmTLB("Stage 2 TLB")
  85
  86     sys = Param.System(Parent.any, "system object parameter")
  87
  88 class ArmStage2IMMU(ArmStage2MMU):
  89     # We rely on the itb being a parameter of the CPU, and get the
  90     # appropriate object that way
  91     tlb = Parent.any
  92     stage2_tlb = ArmStage2TLB()
  93
  94 class ArmStage2DMMU(ArmStage2MMU):
  95     # We rely on the dtb being a parameter of the CPU, and get the
  96     # appropriate object that way
  97     tlb = Parent.any
  98     stage2_tlb = ArmStage2TLB()
  99
 100 class ArmITB(ArmTLB):
 101     stage2_mmu = ArmStage2IMMU()
 102
 103 class ArmDTB(ArmTLB):
 104     stage2_mmu = ArmStage2DMMU()