arm: set ldr_ret_uop as conditional or unconditional control
[gem5.git] / src / arch / arm / ArmTLB.py
1 # -*- mode:python -*-
2
3 # Copyright (c) 2009 ARM Limited
4 # All rights reserved.
5 #
6 # The license below extends only to copyright in the software and shall
7 # not be construed as granting a license to any other intellectual
8 # property including but not limited to intellectual property relating
9 # to a hardware implementation of the functionality of the software
10 # licensed hereunder. You may use the software subject to the license
11 # terms below provided that you ensure that this notice is replicated
12 # unmodified and in its entirety in all distributions of the software,
13 # modified or unmodified, in source code or in binary form.
14 #
15 # Redistribution and use in source and binary forms, with or without
16 # modification, are permitted provided that the following conditions are
17 # met: redistributions of source code must retain the above copyright
18 # notice, this list of conditions and the following disclaimer;
19 # redistributions in binary form must reproduce the above copyright
20 # notice, this list of conditions and the following disclaimer in the
21 # documentation and/or other materials provided with the distribution;
22 # neither the name of the copyright holders nor the names of its
23 # contributors may be used to endorse or promote products derived from
24 # this software without specific prior written permission.
25 #
26 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #
38 # Authors: Ali Saidi
39
40 from m5.SimObject import SimObject
41 from m5.params import *
42 from m5.proxy import *
43 from MemObject import MemObject
44
45 class ArmTableWalker(MemObject):
46 type = 'ArmTableWalker'
47 cxx_class = 'ArmISA::TableWalker'
48 cxx_header = "arch/arm/table_walker.hh"
49 port = MasterPort("Port for TableWalker to do walk the translation with")
50 sys = Param.System(Parent.any, "system object parameter")
51 num_squash_per_cycle = Param.Unsigned(2,
52 "Number of outstanding walks that can be squashed per cycle")
53
54 class ArmTLB(SimObject):
55 type = 'ArmTLB'
56 cxx_class = 'ArmISA::TLB'
57 cxx_header = "arch/arm/tlb.hh"
58 size = Param.Int(64, "TLB size")
59 walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")