3 # Copyright (c) 2009, 2013, 2015 ARM Limited
6 # The license below extends only to copyright in the software and shall
7 # not be construed as granting a license to any other intellectual
8 # property including but not limited to intellectual property relating
9 # to a hardware implementation of the functionality of the software
10 # licensed hereunder. You may use the software subject to the license
11 # terms below provided that you ensure that this notice is replicated
12 # unmodified and in its entirety in all distributions of the software,
13 # modified or unmodified, in source code or in binary form.
15 # Redistribution and use in source and binary forms, with or without
16 # modification, are permitted provided that the following conditions are
17 # met: redistributions of source code must retain the above copyright
18 # notice, this list of conditions and the following disclaimer;
19 # redistributions in binary form must reproduce the above copyright
20 # notice, this list of conditions and the following disclaimer in the
21 # documentation and/or other materials provided with the distribution;
22 # neither the name of the copyright holders nor the names of its
23 # contributors may be used to endorse or promote products derived from
24 # this software without specific prior written permission.
26 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 from m5
.SimObject
import SimObject
41 from m5
.params
import *
42 from m5
.proxy
import *
43 from m5
.objects
.BaseTLB
import BaseTLB
44 from m5
.objects
.ClockedObject
import ClockedObject
46 # Basic stage 1 translation objects
47 class ArmTableWalker(ClockedObject
):
48 type = 'ArmTableWalker'
49 cxx_class
= 'ArmISA::TableWalker'
50 cxx_header
= "arch/arm/table_walker.hh"
51 is_stage2
= Param
.Bool(False, "Is this object for stage 2 translation?")
52 num_squash_per_cycle
= Param
.Unsigned(2,
53 "Number of outstanding walks that can be squashed per cycle")
55 # The port to the memory system. This port is ultimately belonging
56 # to the Stage2MMU, and shared by the two table walkers, but we
57 # access it through the ITB and DTB walked objects in the CPU for
58 # symmetry with the other ISAs.
59 port
= MasterPort("Port used by the two table walkers")
61 sys
= Param
.System(Parent
.any
, "system object parameter")
63 class ArmTLB(BaseTLB
):
65 cxx_class
= 'ArmISA::TLB'
66 cxx_header
= "arch/arm/tlb.hh"
67 sys
= Param
.System(Parent
.any
, "system object parameter")
68 size
= Param
.Int(64, "TLB size")
69 walker
= Param
.ArmTableWalker(ArmTableWalker(), "HW Table walker")
70 is_stage2
= Param
.Bool(False, "Is this a stage 2 TLB?")
72 # Stage 2 translation objects, only used when virtualisation is being used
73 class ArmStage2TableWalker(ArmTableWalker
):
76 class ArmStage2TLB(ArmTLB
):
78 walker
= ArmStage2TableWalker()
81 class ArmStage2MMU(SimObject
):
83 cxx_class
= 'ArmISA::Stage2MMU'
84 cxx_header
= 'arch/arm/stage2_mmu.hh'
85 tlb
= Param
.ArmTLB("Stage 1 TLB")
86 stage2_tlb
= Param
.ArmTLB("Stage 2 TLB")
88 sys
= Param
.System(Parent
.any
, "system object parameter")
90 class ArmStage2IMMU(ArmStage2MMU
):
91 # We rely on the itb being a parameter of the CPU, and get the
92 # appropriate object that way
94 stage2_tlb
= ArmStage2TLB()
96 class ArmStage2DMMU(ArmStage2MMU
):
97 # We rely on the dtb being a parameter of the CPU, and get the
98 # appropriate object that way
100 stage2_tlb
= ArmStage2TLB()
102 class ArmITB(ArmTLB
):
103 stage2_mmu
= ArmStage2IMMU()
105 class ArmDTB(ArmTLB
):
106 stage2_mmu
= ArmStage2DMMU()