src/arch/arm/SConscript

   1 # -*- mode:python -*-
   2
   3 # Copyright (c) 2009, 2012-2013 ARM Limited
   4 # All rights reserved.
   5 #
   6 # The license below extends only to copyright in the software and shall
   7 # not be construed as granting a license to any other intellectual
   8 # property including but not limited to intellectual property relating
   9 # to a hardware implementation of the functionality of the software
  10 # licensed hereunder.  You may use the software subject to the license
  11 # terms below provided that you ensure that this notice is replicated
  12 # unmodified and in its entirety in all distributions of the software,
  13 # modified or unmodified, in source code or in binary form.
  14 #
  15 # Copyright (c) 2007-2008 The Florida State University
  16 # All rights reserved.
  17 #
  18 # Redistribution and use in source and binary forms, with or without
  19 # modification, are permitted provided that the following conditions are
  20 # met: redistributions of source code must retain the above copyright
  21 # notice, this list of conditions and the following disclaimer;
  22 # redistributions in binary form must reproduce the above copyright
  23 # notice, this list of conditions and the following disclaimer in the
  24 # documentation and/or other materials provided with the distribution;
  25 # neither the name of the copyright holders nor the names of its
  26 # contributors may be used to endorse or promote products derived from
  27 # this software without specific prior written permission.
  28 #
  29 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40 #
  41 # Authors: Stephen Hines
  42 #          Ali Saidi
  43
  44 Import('*')
  45
  46 if env['TARGET_ISA'] == 'arm':
  47 # Workaround for bug in SCons version > 0.97d20071212
  48 # Scons bug id: 2006 M5 Bug id: 308
  49     Dir('isa/formats')
  50     Source('decoder.cc')
  51     Source('faults.cc')
  52     Source('insts/branch64.cc')
  53     Source('insts/data64.cc')
  54     Source('insts/macromem.cc')
  55     Source('insts/mem.cc')
  56     Source('insts/mem64.cc')
  57     Source('insts/misc.cc')
  58     Source('insts/misc64.cc')
  59     Source('insts/pred_inst.cc')
  60     Source('insts/pseudo.cc')
  61     Source('insts/static_inst.cc')
  62     Source('insts/vfp.cc')
  63     Source('insts/fplib.cc')
  64     Source('interrupts.cc')
  65     Source('isa.cc')
  66     Source('isa_device.cc')
  67     Source('linux/linux.cc')
  68     Source('linux/process.cc')
  69     Source('linux/system.cc')
  70     Source('miscregs.cc')
  71     Source('nativetrace.cc')
  72     Source('pmu.cc')
  73     Source('process.cc')
  74     Source('remote_gdb.cc')
  75     Source('stacktrace.cc')
  76     Source('system.cc')
  77     Source('table_walker.cc')
  78     Source('stage2_mmu.cc')
  79     Source('stage2_lookup.cc')
  80     Source('tlb.cc')
  81     Source('utility.cc')
  82     Source('vtophys.cc')
  83
  84     SimObject('ArmInterrupts.py')
  85     SimObject('ArmISA.py')
  86     SimObject('ArmNativeTrace.py')
  87     SimObject('ArmSystem.py')
  88     SimObject('ArmTLB.py')
  89     SimObject('ArmPMU.py')
  90
  91     DebugFlag('Arm')
  92     DebugFlag('Decoder', "Instructions returned by the predecoder")
  93     DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
  94     DebugFlag('PMUVerbose', "Performance Monitor")
  95     DebugFlag('TLBVerbose')
  96
  97     # Add files generated by the ISA description.
  98     env.ISADesc('isa/main.isa')