src/arch/arm/SConscript

   1 # -*- mode:python -*-
   2
   3 # Copyright (c) 2007-2008 The Florida State University
   4 # Copyright (c) 2009 ARM Limited
   5 # All rights reserved.
   6 #
   7 # Redistribution and use in source and binary forms, with or without
   8 # modification, are permitted provided that the following conditions are
   9 # met: redistributions of source code must retain the above copyright
  10 # notice, this list of conditions and the following disclaimer;
  11 # redistributions in binary form must reproduce the above copyright
  12 # notice, this list of conditions and the following disclaimer in the
  13 # documentation and/or other materials provided with the distribution;
  14 # neither the name of the copyright holders nor the names of its
  15 # contributors may be used to endorse or promote products derived from
  16 # this software without specific prior written permission.
  17 #
  18 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  24 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  28 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 #
  30 # Authors: Stephen Hines
  31 #          Ali Saidi
  32
  33 Import('*')
  34
  35 if env['TARGET_ISA'] == 'arm':
  36 # Workaround for bug in SCons version > 0.97d20071212
  37 # Scons bug id: 2006 M5 Bug id: 308
  38     Dir('isa/formats')
  39     Source('faults.cc')
  40     Source('insts/branch.cc')
  41     Source('insts/mem.cc')
  42     Source('insts/pred_inst.cc')
  43     Source('insts/static_inst.cc')
  44     Source('nativetrace.cc')
  45     Source('pagetable.cc')
  46     Source('tlb.cc')
  47     Source('vtophys.cc')
  48     Source('utility.cc')
  49
  50     SimObject('ArmNativeTrace.py')
  51     SimObject('ArmTLB.py')
  52
  53     TraceFlag('Arm')
  54     TraceFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
  55     if env['FULL_SYSTEM']:
  56         Source('interrupts.cc')
  57         Source('stacktrace.cc')
  58         Source('system.cc')
  59
  60         SimObject('ArmInterrupts.py')
  61         SimObject('ArmSystem.py')
  62     else:
  63         Source('process.cc')
  64         Source('linux/linux.cc')
  65         Source('linux/process.cc')
  66
  67     # Add in files generated by the ISA description.
  68     isa_desc_files = env.ISADesc('isa/main.isa')
  69     # Only non-header files need to be compiled.
  70     for f in isa_desc_files:
  71         if not f.path.endswith('.hh'):
  72             Source(f)
  73