ARM: Implement a function to decode CP15 registers to MiscReg indices.
[gem5.git] / src / arch / arm / SConscript
1 # -*- mode:python -*-
2
3 # Copyright (c) 2009 ARM Limited
4 # All rights reserved.
5 #
6 # The license below extends only to copyright in the software and shall
7 # not be construed as granting a license to any other intellectual
8 # property including but not limited to intellectual property relating
9 # to a hardware implementation of the functionality of the software
10 # licensed hereunder. You may use the software subject to the license
11 # terms below provided that you ensure that this notice is replicated
12 # unmodified and in its entirety in all distributions of the software,
13 # modified or unmodified, in source code or in binary form.
14 #
15 # Copyright (c) 2007-2008 The Florida State University
16 # All rights reserved.
17 #
18 # Redistribution and use in source and binary forms, with or without
19 # modification, are permitted provided that the following conditions are
20 # met: redistributions of source code must retain the above copyright
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22 # redistributions in binary form must reproduce the above copyright
23 # notice, this list of conditions and the following disclaimer in the
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25 # neither the name of the copyright holders nor the names of its
26 # contributors may be used to endorse or promote products derived from
27 # this software without specific prior written permission.
28 #
29 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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35 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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40 #
41 # Authors: Stephen Hines
42 # Ali Saidi
43
44 Import('*')
45
46 if env['TARGET_ISA'] == 'arm':
47 # Workaround for bug in SCons version > 0.97d20071212
48 # Scons bug id: 2006 M5 Bug id: 308
49 Dir('isa/formats')
50 Source('faults.cc')
51 Source('insts/branch.cc')
52 Source('insts/macromem.cc')
53 Source('insts/mem.cc')
54 Source('insts/misc.cc')
55 Source('insts/pred_inst.cc')
56 Source('insts/static_inst.cc')
57 Source('miscregs.cc')
58 Source('nativetrace.cc')
59 Source('pagetable.cc')
60 Source('tlb.cc')
61 Source('vtophys.cc')
62 Source('utility.cc')
63
64 SimObject('ArmNativeTrace.py')
65 SimObject('ArmTLB.py')
66
67 TraceFlag('Arm')
68 TraceFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
69 TraceFlag('Predecoder', "Instructions returned by the predecoder")
70 if env['FULL_SYSTEM']:
71 Source('interrupts.cc')
72 Source('stacktrace.cc')
73 Source('system.cc')
74
75 SimObject('ArmInterrupts.py')
76 SimObject('ArmSystem.py')
77 else:
78 Source('process.cc')
79 Source('linux/linux.cc')
80 Source('linux/process.cc')
81
82 # Add in files generated by the ISA description.
83 isa_desc_files = env.ISADesc('isa/main.isa')
84 # Only non-header files need to be compiled.
85 for f in isa_desc_files:
86 if not f.path.endswith('.hh'):
87 Source(f)
88