src/arch/arm/decoder.hh

   1 /*
   2  * Copyright (c) 2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2012 Google
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Gabe Black
  41  */
  42
  43 #ifndef __ARCH_ARM_DECODER_HH__
  44 #define __ARCH_ARM_DECODER_HH__
  45
  46 #include <cassert>
  47
  48 #include "arch/arm/miscregs.hh"
  49 #include "arch/arm/types.hh"
  50 #include "arch/generic/decode_cache.hh"
  51 #include "base/types.hh"
  52 #include "cpu/static_inst.hh"
  53
  54 namespace ArmISA
  55 {
  56
  57 class Decoder
  58 {
  59   protected:
  60     //The extended machine instruction being generated
  61     ExtMachInst emi;
  62     MachInst data;
  63     bool bigThumb;
  64     bool instDone;
  65     bool outOfBytes;
  66     int offset;
  67     bool foundIt;
  68     ITSTATE itBits;
  69
  70     int fpscrLen;
  71     int fpscrStride;
  72
  73   public:
  74     void reset()
  75     {
  76         bigThumb = false;
  77         offset = 0;
  78         emi = 0;
  79         instDone = false;
  80         outOfBytes = true;
  81         foundIt = false;
  82     }
  83
  84     Decoder() : data(0), fpscrLen(0), fpscrStride(0)
  85     {
  86         reset();
  87     }
  88
  89     void process();
  90
  91     //Use this to give data to the decoder. This should be used
  92     //when there is control flow.
  93     void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
  94
  95     //Use this to give data to the decoder. This should be used
  96     //when instructions are executed in order.
  97     void moreBytes(MachInst machInst)
  98     {
  99         moreBytes(0, 0, machInst);
 100     }
 101
 102     inline void consumeBytes(int numBytes)
 103     {
 104         offset += numBytes;
 105         assert(offset <= sizeof(MachInst));
 106         if (offset == sizeof(MachInst))
 107             outOfBytes = true;
 108     }
 109
 110     bool needMoreBytes() const
 111     {
 112         return outOfBytes;
 113     }
 114
 115     bool instReady() const
 116     {
 117         return instDone;
 118     }
 119
 120     int getInstSize() const
 121     {
 122         return (!emi.thumb || emi.bigThumb) ? 4 : 2;
 123     }
 124
 125     void setContext(FPSCR fpscr)
 126     {
 127         fpscrLen = fpscr.len;
 128         fpscrStride = fpscr.stride;
 129     }
 130
 131     void takeOverFrom(Decoder *old) {}
 132
 133   protected:
 134     /// A cache of decoded instruction objects.
 135     static GenericISA::BasicDecodeCache defaultCache;
 136
 137   public:
 138     StaticInstPtr decodeInst(ExtMachInst mach_inst);
 139
 140     /// Decode a machine instruction.
 141     /// @param mach_inst The binary instruction to decode.
 142     /// @retval A pointer to the corresponding StaticInst object.
 143     StaticInstPtr
 144     decode(ExtMachInst mach_inst, Addr addr)
 145     {
 146         return defaultCache.decode(this, mach_inst, addr);
 147     }
 148
 149     StaticInstPtr
 150     decode(ArmISA::PCState &nextPC)
 151     {
 152         if (!instDone)
 153             return NULL;
 154
 155         assert(instDone);
 156         ExtMachInst thisEmi = emi;
 157         nextPC.npc(nextPC.pc() + getInstSize());
 158         if (foundIt)
 159             nextPC.nextItstate(itBits);
 160         thisEmi.itstate = nextPC.itstate();
 161         nextPC.size(getInstSize());
 162         emi = 0;
 163         instDone = false;
 164         foundIt = false;
 165         return decode(thisEmi, nextPC.instAddr());
 166     }
 167 };
 168
 169 } // namespace ArmISA
 170
 171 #endif // __ARCH_ARM_DECODER_HH__