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43 #ifndef __ARCH_ARM_DECODER_HH__
44 #define __ARCH_ARM_DECODER_HH__
48 #include "arch/arm/miscregs.hh"
49 #include "arch/arm/types.hh"
50 #include "arch/generic/decode_cache.hh"
51 #include "base/types.hh"
52 #include "cpu/static_inst.hh"
60 //The extended machine instruction being generated
84 Decoder() : data(0), fpscrLen(0), fpscrStride(0)
91 //Use this to give data to the decoder. This should be used
92 //when there is control flow.
93 void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
95 //Use this to give data to the decoder. This should be used
96 //when instructions are executed in order.
97 void moreBytes(MachInst machInst)
99 moreBytes(0, 0, machInst);
102 inline void consumeBytes(int numBytes)
105 assert(offset <= sizeof(MachInst));
106 if (offset == sizeof(MachInst))
110 bool needMoreBytes() const
115 bool instReady() const
120 int getInstSize() const
122 return (!emi.thumb || emi.bigThumb) ? 4 : 2;
125 void setContext(FPSCR fpscr)
127 fpscrLen = fpscr.len;
128 fpscrStride = fpscr.stride;
131 void takeOverFrom(Decoder *old) {}
134 /// A cache of decoded instruction objects.
135 static GenericISA::BasicDecodeCache defaultCache;
138 StaticInstPtr decodeInst(ExtMachInst mach_inst);
140 /// Decode a machine instruction.
141 /// @param mach_inst The binary instruction to decode.
142 /// @retval A pointer to the corresponding StaticInst object.
144 decode(ExtMachInst mach_inst, Addr addr)
146 return defaultCache.decode(this, mach_inst, addr);
150 decode(ArmISA::PCState &nextPC)
156 ExtMachInst thisEmi = emi;
157 nextPC.npc(nextPC.pc() + getInstSize());
159 nextPC.nextItstate(itBits);
160 thisEmi.itstate = nextPC.itstate();
161 nextPC.size(getInstSize());
165 return decode(thisEmi, nextPC.instAddr());
169 } // namespace ArmISA
171 #endif // __ARCH_ARM_DECODER_HH__