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31 #ifndef __ARCH_ARM_DECODER_HH__
32 #define __ARCH_ARM_DECODER_HH__
36 #include "arch/arm/miscregs.hh"
37 #include "arch/arm/types.hh"
38 #include "arch/generic/decode_cache.hh"
39 #include "base/types.hh"
40 #include "cpu/static_inst.hh"
48 //The extended machine instruction being generated
72 Decoder() : data(0), fpscrLen(0), fpscrStride(0)
79 //Use this to give data to the decoder. This should be used
80 //when there is control flow.
81 void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
83 //Use this to give data to the decoder. This should be used
84 //when instructions are executed in order.
85 void moreBytes(MachInst machInst)
87 moreBytes(0, 0, machInst);
90 inline void consumeBytes(int numBytes)
93 assert(offset <= sizeof(MachInst));
94 if (offset == sizeof(MachInst))
98 bool needMoreBytes() const
103 bool instReady() const
108 int getInstSize() const
110 return (!emi.thumb || emi.bigThumb) ? 4 : 2;
113 void setContext(FPSCR fpscr)
115 fpscrLen = fpscr.len;
116 fpscrStride = fpscr.stride;
119 void takeOverFrom(Decoder *old) {}
122 /// A cache of decoded instruction objects.
123 static GenericISA::BasicDecodeCache defaultCache;
126 StaticInstPtr decodeInst(ExtMachInst mach_inst);
128 /// Decode a machine instruction.
129 /// @param mach_inst The binary instruction to decode.
130 /// @retval A pointer to the corresponding StaticInst object.
132 decode(ExtMachInst mach_inst, Addr addr)
134 return defaultCache.decode(this, mach_inst, addr);
138 decode(ArmISA::PCState &nextPC)
144 ExtMachInst thisEmi = emi;
145 nextPC.npc(nextPC.pc() + getInstSize());
147 nextPC.nextItstate(itBits);
148 thisEmi.itstate = nextPC.itstate();
149 nextPC.size(getInstSize());
153 return decode(thisEmi, nextPC.instAddr());
157 } // namespace ArmISA
159 #endif // __ARCH_ARM_DECODER_HH__