src/arch/arm/decoder.hh

   1 /*
   2  * Copyright (c) 2012 Google
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 #ifndef __ARCH_ARM_DECODER_HH__
  32 #define __ARCH_ARM_DECODER_HH__
  33
  34 #include <cassert>
  35
  36 #include "arch/arm/miscregs.hh"
  37 #include "arch/arm/types.hh"
  38 #include "arch/generic/decode_cache.hh"
  39 #include "base/types.hh"
  40 #include "cpu/static_inst.hh"
  41
  42 namespace ArmISA
  43 {
  44
  45 class Decoder
  46 {
  47   protected:
  48     //The extended machine instruction being generated
  49     ExtMachInst emi;
  50     MachInst data;
  51     bool bigThumb;
  52     bool instDone;
  53     bool outOfBytes;
  54     int offset;
  55     bool foundIt;
  56     ITSTATE itBits;
  57
  58     int fpscrLen;
  59     int fpscrStride;
  60
  61   public:
  62     void reset()
  63     {
  64         bigThumb = false;
  65         offset = 0;
  66         emi = 0;
  67         instDone = false;
  68         outOfBytes = true;
  69         foundIt = false;
  70     }
  71
  72     Decoder() : data(0), fpscrLen(0), fpscrStride(0)
  73     {
  74         reset();
  75     }
  76
  77     void process();
  78
  79     //Use this to give data to the decoder. This should be used
  80     //when there is control flow.
  81     void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
  82
  83     //Use this to give data to the decoder. This should be used
  84     //when instructions are executed in order.
  85     void moreBytes(MachInst machInst)
  86     {
  87         moreBytes(0, 0, machInst);
  88     }
  89
  90     inline void consumeBytes(int numBytes)
  91     {
  92         offset += numBytes;
  93         assert(offset <= sizeof(MachInst));
  94         if (offset == sizeof(MachInst))
  95             outOfBytes = true;
  96     }
  97
  98     bool needMoreBytes() const
  99     {
 100         return outOfBytes;
 101     }
 102
 103     bool instReady() const
 104     {
 105         return instDone;
 106     }
 107
 108     int getInstSize() const
 109     {
 110         return (!emi.thumb || emi.bigThumb) ? 4 : 2;
 111     }
 112
 113     void setContext(FPSCR fpscr)
 114     {
 115         fpscrLen = fpscr.len;
 116         fpscrStride = fpscr.stride;
 117     }
 118
 119   protected:
 120     /// A cache of decoded instruction objects.
 121     static GenericISA::BasicDecodeCache defaultCache;
 122
 123   public:
 124     StaticInstPtr decodeInst(ExtMachInst mach_inst);
 125
 126     /// Decode a machine instruction.
 127     /// @param mach_inst The binary instruction to decode.
 128     /// @retval A pointer to the corresponding StaticInst object.
 129     StaticInstPtr
 130     decode(ExtMachInst mach_inst, Addr addr)
 131     {
 132         return defaultCache.decode(this, mach_inst, addr);
 133     }
 134
 135     StaticInstPtr
 136     decode(ArmISA::PCState &nextPC)
 137     {
 138         if (!instDone)
 139             return NULL;
 140
 141         assert(instDone);
 142         ExtMachInst thisEmi = emi;
 143         nextPC.npc(nextPC.pc() + getInstSize());
 144         if (foundIt)
 145             nextPC.nextItstate(itBits);
 146         thisEmi.itstate = nextPC.itstate();
 147         nextPC.size(getInstSize());
 148         emi = 0;
 149         instDone = false;
 150         foundIt = false;
 151         return decode(thisEmi, nextPC.instAddr());
 152     }
 153 };
 154
 155 } // namespace ArmISA
 156
 157 #endif // __ARCH_ARM_DECODER_HH__