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43 #ifndef __ARCH_ARM_DECODER_HH__
44 #define __ARCH_ARM_DECODER_HH__
48 #include "arch/arm/miscregs.hh"
49 #include "arch/arm/types.hh"
50 #include "arch/generic/decode_cache.hh"
51 #include "base/types.hh"
52 #include "cpu/static_inst.hh"
53 #include "enums/DecoderFlavour.hh"
62 //The extended machine instruction being generated
76 * SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN
81 Enums::DecoderFlavour decoderFlavour;
83 /// A cache of decoded instruction objects.
84 static GenericISA::BasicDecodeCache defaultCache;
87 * Pre-decode an instruction from the current state of the
93 * Consume bytes by moving the offset into the data word and
94 * sanity check the results.
96 void consumeBytes(int numBytes);
98 public: // Decoder API
99 Decoder(ISA* isa = nullptr);
101 /** Reset the decoders internal state. */
105 * Can the decoder accept more data?
107 * A CPU model uses this method to determine if the decoder can
108 * accept more data. Note that an instruction can be ready (see
109 * instReady() even if this method returns true.
111 bool needMoreBytes() const { return outOfBytes; }
114 * Is an instruction ready to be decoded?
116 * CPU models call this method to determine if decode() will
117 * return a new instruction on the next call. It typically only
118 * returns false if the decoder hasn't received enough data to
119 * decode a full instruction.
121 bool instReady() const { return instDone; }
124 * Feed data to the decoder.
126 * A CPU model uses this interface to load instruction data into
127 * the decoder. Once enough data has been loaded (check with
128 * instReady()), a decoded instruction can be retrieved using
129 * decode(ArmISA::PCState).
131 * This method is intended to support both fixed-length and
132 * variable-length instructions. Instruction data is fetch in
133 * MachInst blocks (which correspond to the size of a typical
134 * insturction). The method might need to be called multiple times
135 * if the instruction spans multiple blocks, in that case
136 * needMoreBytes() will return true and instReady() will return
139 * The fetchPC parameter is used to indicate where in memory the
140 * instruction was fetched from. This is should be the same
141 * address as the pc. If fetching multiple blocks, it indicates
142 * where subsequent blocks are fetched from (pc + n *
145 * @param pc Instruction pointer that we are decoding.
146 * @param fetchPC The address this chunk was fetched from.
147 * @param inst Raw instruction data.
149 void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
152 * Decode an instruction or fetch it from the code cache.
154 * This method decodes the currently pending pre-decoded
155 * instruction. Data must be fed to the decoder using moreBytes()
156 * until instReady() is true before calling this method.
158 * @param pc Instruction pointer that we are decoding.
159 * @return A pointer to a static instruction or NULL if the
160 * decoder isn't ready (see instReady()).
162 StaticInstPtr decode(ArmISA::PCState &pc);
165 * Decode a pre-decoded machine instruction.
167 * @warn This method takes a pre-decoded instruction as its
168 * argument. It should typically not be called directly.
170 * @param mach_inst A pre-decoded instruction
171 * @retval A pointer to the corresponding StaticInst object.
173 StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
175 return defaultCache.decode(this, mach_inst, addr);
179 * Decode a machine instruction without calling the cache.
181 * @note The implementation of this method is generated by the ISA
184 * @warn This method takes a pre-decoded instruction as its
185 * argument. It should typically not be called directly.
187 * @param mach_inst The binary instruction to decode.
188 * @retval A pointer to the corresponding StaticInst object.
190 StaticInstPtr decodeInst(ExtMachInst mach_inst);
193 * Take over the state from an old decoder when switching CPUs.
195 * @param old Decoder used in old CPU
197 void takeOverFrom(Decoder *old) {}
200 public: // ARM-specific decoder state manipulation
201 void setContext(FPSCR fpscr)
203 fpscrLen = fpscr.len;
204 fpscrStride = fpscr.stride;
207 void setSveLen(uint8_t len)
213 } // namespace ArmISA
215 #endif // __ARCH_ARM_DECODER_HH__