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43 #ifndef __ARCH_ARM_DECODER_HH__
44 #define __ARCH_ARM_DECODER_HH__
48 #include "arch/arm/miscregs.hh"
49 #include "arch/arm/types.hh"
50 #include "arch/generic/decode_cache.hh"
51 #include "base/types.hh"
52 #include "cpu/static_inst.hh"
53 #include "enums/DecoderFlavour.hh"
62 //The extended machine instruction being generated
75 Enums::DecoderFlavour decoderFlavour;
77 /// A cache of decoded instruction objects.
78 static GenericISA::BasicDecodeCache defaultCache;
81 * Pre-decode an instruction from the current state of the
87 * Consume bytes by moving the offset into the data word and
88 * sanity check the results.
90 void consumeBytes(int numBytes);
92 public: // Decoder API
93 Decoder(ISA* isa = nullptr);
95 /** Reset the decoders internal state. */
99 * Can the decoder accept more data?
101 * A CPU model uses this method to determine if the decoder can
102 * accept more data. Note that an instruction can be ready (see
103 * instReady() even if this method returns true.
105 bool needMoreBytes() const { return outOfBytes; }
108 * Is an instruction ready to be decoded?
110 * CPU models call this method to determine if decode() will
111 * return a new instruction on the next call. It typically only
112 * returns false if the decoder hasn't received enough data to
113 * decode a full instruction.
115 bool instReady() const { return instDone; }
118 * Feed data to the decoder.
120 * A CPU model uses this interface to load instruction data into
121 * the decoder. Once enough data has been loaded (check with
122 * instReady()), a decoded instruction can be retrieved using
123 * decode(ArmISA::PCState).
125 * This method is intended to support both fixed-length and
126 * variable-length instructions. Instruction data is fetch in
127 * MachInst blocks (which correspond to the size of a typical
128 * insturction). The method might need to be called multiple times
129 * if the instruction spans multiple blocks, in that case
130 * needMoreBytes() will return true and instReady() will return
133 * The fetchPC parameter is used to indicate where in memory the
134 * instruction was fetched from. This is should be the same
135 * address as the pc. If fetching multiple blocks, it indicates
136 * where subsequent blocks are fetched from (pc + n *
139 * @param pc Instruction pointer that we are decoding.
140 * @param fetchPC The address this chunk was fetched from.
141 * @param inst Raw instruction data.
143 void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
146 * Decode an instruction or fetch it from the code cache.
148 * This method decodes the currently pending pre-decoded
149 * instruction. Data must be fed to the decoder using moreBytes()
150 * until instReady() is true before calling this method.
152 * @param pc Instruction pointer that we are decoding.
153 * @return A pointer to a static instruction or NULL if the
154 * decoder isn't ready (see instReady()).
156 StaticInstPtr decode(ArmISA::PCState &pc);
159 * Decode a pre-decoded machine instruction.
161 * @warn This method takes a pre-decoded instruction as its
162 * argument. It should typically not be called directly.
164 * @param mach_inst A pre-decoded instruction
165 * @retval A pointer to the corresponding StaticInst object.
167 StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
169 return defaultCache.decode(this, mach_inst, addr);
173 * Decode a machine instruction without calling the cache.
175 * @note The implementation of this method is generated by the ISA
178 * @warn This method takes a pre-decoded instruction as its
179 * argument. It should typically not be called directly.
181 * @param mach_inst The binary instruction to decode.
182 * @retval A pointer to the corresponding StaticInst object.
184 StaticInstPtr decodeInst(ExtMachInst mach_inst);
187 * Take over the state from an old decoder when switching CPUs.
189 * @param old Decoder used in old CPU
191 void takeOverFrom(Decoder *old) {}
194 public: // ARM-specific decoder state manipulation
195 void setContext(FPSCR fpscr)
197 fpscrLen = fpscr.len;
198 fpscrStride = fpscr.stride;
202 } // namespace ArmISA
204 #endif // __ARCH_ARM_DECODER_HH__