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31 #ifndef __ARCH_ARM_DECODER_HH__
32 #define __ARCH_ARM_DECODER_HH__
36 #include "arch/arm/miscregs.hh"
37 #include "arch/arm/types.hh"
38 #include "base/types.hh"
39 #include "cpu/decode_cache.hh"
50 //The extended machine instruction being generated
71 Decoder(ThreadContext * _tc) : tc(_tc), data(0)
76 ThreadContext * getTC()
82 setTC(ThreadContext * _tc)
89 //Use this to give data to the decoder. This should be used
90 //when there is control flow.
91 void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
93 //Use this to give data to the decoder. This should be used
94 //when instructions are executed in order.
95 void moreBytes(MachInst machInst)
97 moreBytes(0, 0, machInst);
100 inline void consumeBytes(int numBytes)
103 assert(offset <= sizeof(MachInst));
104 if (offset == sizeof(MachInst))
108 bool needMoreBytes() const
113 bool instReady() const
118 int getInstSize() const
120 return (!emi.thumb || emi.bigThumb) ? 4 : 2;
124 /// A cache of decoded instruction objects.
125 static DecodeCache defaultCache;
128 StaticInstPtr decodeInst(ExtMachInst mach_inst);
130 /// Decode a machine instruction.
131 /// @param mach_inst The binary instruction to decode.
132 /// @retval A pointer to the corresponding StaticInst object.
134 decode(ExtMachInst mach_inst, Addr addr)
136 return defaultCache.decode(this, mach_inst, addr);
140 decode(ArmISA::PCState &nextPC)
146 ExtMachInst thisEmi = emi;
147 nextPC.npc(nextPC.pc() + getInstSize());
149 nextPC.nextItstate(itBits);
150 thisEmi.itstate = nextPC.itstate();
151 nextPC.size(getInstSize());
155 return decode(thisEmi, nextPC.instAddr());
159 } // namespace ArmISA
161 #endif // __ARCH_ARM_DECODER_HH__