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41 #ifndef __ARCH_ARM_DECODER_HH__
42 #define __ARCH_ARM_DECODER_HH__
46 #include "arch/arm/miscregs.hh"
47 #include "arch/arm/types.hh"
48 #include "arch/generic/decode_cache.hh"
49 #include "arch/generic/decoder.hh"
50 #include "base/types.hh"
51 #include "cpu/static_inst.hh"
52 #include "enums/DecoderFlavor.hh"
58 class Decoder : public InstDecoder
61 //The extended machine instruction being generated
75 * SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN
80 Enums::DecoderFlavor decoderFlavor;
82 /// A cache of decoded instruction objects.
83 static GenericISA::BasicDecodeCache defaultCache;
86 * Pre-decode an instruction from the current state of the
92 * Consume bytes by moving the offset into the data word and
93 * sanity check the results.
95 void consumeBytes(int numBytes);
97 public: // Decoder API
98 Decoder(ISA* isa = nullptr);
100 /** Reset the decoders internal state. */
104 * Can the decoder accept more data?
106 * A CPU model uses this method to determine if the decoder can
107 * accept more data. Note that an instruction can be ready (see
108 * instReady() even if this method returns true.
110 bool needMoreBytes() const { return outOfBytes; }
113 * Is an instruction ready to be decoded?
115 * CPU models call this method to determine if decode() will
116 * return a new instruction on the next call. It typically only
117 * returns false if the decoder hasn't received enough data to
118 * decode a full instruction.
120 bool instReady() const { return instDone; }
123 * Feed data to the decoder.
125 * A CPU model uses this interface to load instruction data into
126 * the decoder. Once enough data has been loaded (check with
127 * instReady()), a decoded instruction can be retrieved using
128 * decode(ArmISA::PCState).
130 * This method is intended to support both fixed-length and
131 * variable-length instructions. Instruction data is fetch in
132 * MachInst blocks (which correspond to the size of a typical
133 * insturction). The method might need to be called multiple times
134 * if the instruction spans multiple blocks, in that case
135 * needMoreBytes() will return true and instReady() will return
138 * The fetchPC parameter is used to indicate where in memory the
139 * instruction was fetched from. This is should be the same
140 * address as the pc. If fetching multiple blocks, it indicates
141 * where subsequent blocks are fetched from (pc + n *
144 * @param pc Instruction pointer that we are decoding.
145 * @param fetchPC The address this chunk was fetched from.
146 * @param inst Raw instruction data.
148 void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
151 * Decode an instruction or fetch it from the code cache.
153 * This method decodes the currently pending pre-decoded
154 * instruction. Data must be fed to the decoder using moreBytes()
155 * until instReady() is true before calling this method.
157 * @param pc Instruction pointer that we are decoding.
158 * @return A pointer to a static instruction or NULL if the
159 * decoder isn't ready (see instReady()).
161 StaticInstPtr decode(ArmISA::PCState &pc);
164 * Decode a pre-decoded machine instruction.
166 * @warn This method takes a pre-decoded instruction as its
167 * argument. It should typically not be called directly.
169 * @param mach_inst A pre-decoded instruction
170 * @retval A pointer to the corresponding StaticInst object.
172 StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
174 return defaultCache.decode(this, mach_inst, addr);
178 * Decode a machine instruction without calling the cache.
180 * @note The implementation of this method is generated by the ISA
183 * @warn This method takes a pre-decoded instruction as its
184 * argument. It should typically not be called directly.
186 * @param mach_inst The binary instruction to decode.
187 * @retval A pointer to the corresponding StaticInst object.
189 StaticInstPtr decodeInst(ExtMachInst mach_inst);
192 * Take over the state from an old decoder when switching CPUs.
194 * @param old Decoder used in old CPU
196 void takeOverFrom(Decoder *old) {}
199 public: // ARM-specific decoder state manipulation
200 void setContext(FPSCR fpscr)
202 fpscrLen = fpscr.len;
203 fpscrStride = fpscr.stride;
206 void setSveLen(uint8_t len)
212 } // namespace ArmISA
214 #endif // __ARCH_ARM_DECODER_HH__