src/arch/arm/fastmodel/CortexA76/cortex_a76.hh

   1 /*
   2  * Copyright 2019 Google, Inc.
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  13  * this software without specific prior written permission.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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  27
  28 #ifndef __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__
  29 #define __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__
  30
  31 #include "arch/arm/fastmodel/CortexA76/thread_context.hh"
  32 #include "arch/arm/fastmodel/amba_ports.hh"
  33 #include "arch/arm/fastmodel/iris/cpu.hh"
  34 #include "params/FastModelCortexA76.hh"
  35 #include "params/FastModelCortexA76Cluster.hh"
  36 #include "scx/scx.h"
  37 #include "sim/port.hh"
  38 #include "systemc/ext/core/sc_module.hh"
  39
  40 class BaseCPU;
  41
  42 namespace FastModel
  43 {
  44
  45 // The fast model exports a class called scx_evs_CortexA76x1 which represents
  46 // the subsystem described in LISA+. This class specializes it to export gem5
  47 // ports and interface with its peer gem5 CPU. The gem5 CPU inherits from the
  48 // gem5 BaseCPU class and implements its API, while this class actually does
  49 // the work.
  50 class CortexA76Cluster;
  51
  52 class CortexA76 : public Iris::CPU<CortexA76TC>
  53 {
  54   protected:
  55     typedef FastModelCortexA76Params Params;
  56     typedef Iris::CPU<CortexA76TC> Base;
  57     const Params &_params;
  58
  59     CortexA76Cluster *cluster = nullptr;
  60     int num = 0;
  61
  62     const Params &params() { return _params; }
  63
  64   public:
  65     CortexA76(const Params &p) :
  66         Base(p, scx::scx_get_iris_connection_interface()), _params(p)
  67     {}
  68
  69     void
  70     clockPeriodUpdated() override
  71     {
  72         Base::clockPeriodUpdated();
  73
  74         // FIXME(b/139447397): this is a workaround since CNTFRQ_EL0 should not
  75         // be modified after clock is changed in real hardwares. Remove or
  76         // modify this after a more reasonable solution is found.
  77         for (auto *tc : threadContexts) {
  78             tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0, frequency());
  79         }
  80     }
  81
  82     void initState() override;
  83
  84     template <class T>
  85     void set_evs_param(const std::string &n, T val);
  86
  87     void setCluster(CortexA76Cluster *_cluster, int _num);
  88
  89     Port &getPort(const std::string &if_name,
  90             PortID idx=InvalidPortID) override;
  91 };
  92
  93 class CortexA76Cluster : public SimObject
  94 {
  95   private:
  96     typedef FastModelCortexA76ClusterParams Params;
  97     const Params &_params;
  98
  99     std::vector<CortexA76 *> cores;
 100     sc_core::sc_module *evs;
 101
 102   public:
 103     template <class T>
 104     void
 105     set_evs_param(const std::string &n, T val)
 106     {
 107         scx::scx_set_parameter(evs->name() + std::string(".") + n, val);
 108     }
 109
 110     CortexA76 *getCore(int num) const { return cores.at(num); }
 111     sc_core::sc_module *getEvs() const { return evs; }
 112
 113     CortexA76Cluster(const Params &p);
 114     const Params &params() { return _params; }
 115
 116     Port &getPort(const std::string &if_name,
 117             PortID idx=InvalidPortID) override;
 118 };
 119
 120 template <class T>
 121 inline void
 122 CortexA76::set_evs_param(const std::string &n, T val)
 123 {
 124     for (auto &path: params().thread_paths)
 125         cluster->set_evs_param(path + "." + n, val);
 126 }
 127
 128 } // namespace FastModel
 129
 130 #endif // __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__