src/arch/arm/fastmodel/CortexA76/cortex_a76.hh

   1 /*
   2  * Copyright 2019 Google, Inc.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions are
   6  * met: redistributions of source code must retain the above copyright
   7  * notice, this list of conditions and the following disclaimer;
   8  * redistributions in binary form must reproduce the above copyright
   9  * notice, this list of conditions and the following disclaimer in the
  10  * documentation and/or other materials provided with the distribution;
  11  * neither the name of the copyright holders nor the names of its
  12  * contributors may be used to endorse or promote products derived from
  13  * this software without specific prior written permission.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  * Authors: Gabe Black
  28  */
  29
  30 #ifndef __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__
  31 #define __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__
  32
  33 #include "arch/arm/fastmodel/CortexA76/thread_context.hh"
  34 #include "arch/arm/fastmodel/amba_ports.hh"
  35 #include "arch/arm/fastmodel/iris/cpu.hh"
  36 #include "params/FastModelCortexA76.hh"
  37 #include "params/FastModelCortexA76Cluster.hh"
  38 #include "scx/scx.h"
  39 #include "sim/port.hh"
  40 #include "systemc/ext/core/sc_module.hh"
  41
  42 class BaseCPU;
  43
  44 namespace FastModel
  45 {
  46
  47 // The fast model exports a class called scx_evs_CortexA76x1 which represents
  48 // the subsystem described in LISA+. This class specializes it to export gem5
  49 // ports and interface with its peer gem5 CPU. The gem5 CPU inherits from the
  50 // gem5 BaseCPU class and implements its API, while this class actually does
  51 // the work.
  52 class CortexA76Cluster;
  53
  54 class CortexA76 : public Iris::CPU<CortexA76TC>
  55 {
  56   protected:
  57     typedef FastModelCortexA76Params Params;
  58     typedef Iris::CPU<CortexA76TC> Base;
  59     const Params &_params;
  60
  61     CortexA76Cluster *cluster = nullptr;
  62     int num = 0;
  63
  64     const Params &params() { return _params; }
  65
  66   public:
  67     CortexA76(Params &p) : Base(&p, scx::scx_get_iris_connection_interface()),
  68         _params(p)
  69     {}
  70
  71     void
  72     clockPeriodUpdated() override
  73     {
  74         Base::clockPeriodUpdated();
  75
  76         // FIXME(b/139447397): this is a workaround since CNTFRQ_EL0 should not
  77         // be modified after clock is changed in real hardwares. Remove or
  78         // modify this after a more reasonable solution is found.
  79         for (auto *tc : threadContexts) {
  80             tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0, frequency());
  81         }
  82     }
  83
  84     void initState() override;
  85
  86     template <class T>
  87     void set_evs_param(const std::string &n, T val);
  88
  89     void setCluster(CortexA76Cluster *_cluster, int _num);
  90
  91     Port &getPort(const std::string &if_name,
  92             PortID idx=InvalidPortID) override;
  93 };
  94
  95 class CortexA76Cluster : public SimObject
  96 {
  97   private:
  98     typedef FastModelCortexA76ClusterParams Params;
  99     const Params &_params;
 100
 101     std::vector<CortexA76 *> cores;
 102     sc_core::sc_module *evs;
 103
 104   public:
 105     template <class T>
 106     void
 107     set_evs_param(const std::string &n, T val)
 108     {
 109         scx::scx_set_parameter(evs->name() + std::string(".") + n, val);
 110     }
 111
 112     CortexA76 *getCore(int num) { return cores.at(num); }
 113     sc_core::sc_module *getEvs() { return evs; }
 114
 115     CortexA76Cluster(Params &p);
 116     const Params &params() { return _params; }
 117
 118     Port &getPort(const std::string &if_name,
 119             PortID idx=InvalidPortID) override;
 120 };
 121
 122 template <class T>
 123 inline void
 124 CortexA76::set_evs_param(const std::string &n, T val)
 125 {
 126     for (auto &path: params().thread_paths)
 127         cluster->set_evs_param(path + "." + n, val);
 128 }
 129
 130 } // namespace FastModel
 131
 132 #endif // __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__