src/arch/arm/fastmodel/CortexR52/cortex_r52.cc

   1 /*
   2  * Copyright 2020 Google, Inc.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions are
   6  * met: redistributions of source code must retain the above copyright
   7  * notice, this list of conditions and the following disclaimer;
   8  * redistributions in binary form must reproduce the above copyright
   9  * notice, this list of conditions and the following disclaimer in the
  10  * documentation and/or other materials provided with the distribution;
  11  * neither the name of the copyright holders nor the names of its
  12  * contributors may be used to endorse or promote products derived from
  13  * this software without specific prior written permission.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "arch/arm/fastmodel/CortexR52/cortex_r52.hh"
  29
  30 #include "arch/arm/fastmodel/iris/cpu.hh"
  31 #include "base/logging.hh"
  32 #include "dev/arm/base_gic.hh"
  33 #include "sim/core.hh"
  34 #include "systemc/tlm_bridge/gem5_to_tlm.hh"
  35
  36 namespace FastModel
  37 {
  38
  39 void
  40 CortexR52::setCluster(CortexR52Cluster *_cluster, int _num)
  41 {
  42     cluster = _cluster;
  43     num = _num;
  44
  45     set_evs_param("CFGEND", params().CFGEND);
  46     set_evs_param("CFGTE", params().CFGTE);
  47     set_evs_param("RVBARADDR", params().RVBARADDR);
  48     set_evs_param("ase-present", params().ase_present);
  49     set_evs_param("dcache-size", params().dcache_size);
  50     set_evs_param("flash.enable", params().flash_enable);
  51     set_evs_param("icache-size", params().icache_size);
  52     set_evs_param("llpp.base", params().llpp_base);
  53     set_evs_param("llpp.size", params().llpp_size);
  54     set_evs_param("max_code_cache_mb", params().max_code_cache_mb);
  55     set_evs_param("min_sync_level", params().min_sync_level);
  56     set_evs_param("semihosting-A32_HLT", params().semihosting_A32_HLT);
  57     // Use uint32_t, since the model doesn't like setting these as uint8_t.
  58     set_evs_param<uint32_t>("semihosting-ARM_SVC",
  59             params().semihosting_ARM_SVC);
  60     set_evs_param<uint32_t>("semihosting-T32_HLT",
  61             params().semihosting_T32_HLT);
  62     set_evs_param<uint32_t>("semihosting-Thumb_SVC",
  63             params().semihosting_Thumb_SVC);
  64     set_evs_param("semihosting-cmd_line", params().semihosting_cmd_line);
  65     set_evs_param("semihosting-cwd", params().semihosting_cwd);
  66     set_evs_param("semihosting-enable", params().semihosting_enable);
  67     set_evs_param("semihosting-heap_base", params().semihosting_heap_base);
  68     set_evs_param("semihosting-heap_limit", params().semihosting_heap_limit);
  69     set_evs_param("semihosting-stack_base", params().semihosting_stack_base);
  70     set_evs_param("semihosting-stack_limit", params().semihosting_stack_limit);
  71     set_evs_param("tcm.a.enable", params().tcm_a_enable);
  72     set_evs_param("tcm.a.size", params().tcm_a_size);
  73     set_evs_param("tcm.b.size", params().tcm_b_size);
  74     set_evs_param("tcm.c.size", params().tcm_c_size);
  75     set_evs_param("vfp-dp-present", params().vfp_dp_present);
  76     set_evs_param("vfp-enable_at_reset", params().vfp_enable_at_reset);
  77 }
  78
  79 Port &
  80 CortexR52::getPort(const std::string &if_name, PortID idx)
  81 {
  82     if (if_name == "ppi") {
  83         // Since PPIs are indexed both by core and by number, modify the name
  84         // to hold the core number.
  85         return evs->gem5_getPort(csprintf("%s_%d", if_name, num), idx);
  86     } else if (if_name == "amba" || if_name == "llpp" || if_name == "flash") {
  87         // Since these ports are scalar per core, use the core number as the
  88         // index. Also verify that that index is not being used.
  89         assert(idx == InvalidPortID);
  90         return evs->gem5_getPort(if_name, num);
  91     } else {
  92         return SimObject::getPort(if_name, idx);
  93     }
  94 }
  95
  96 CortexR52Cluster::CortexR52Cluster(const Params &p) :
  97     SimObject(p), _params(p), cores(p.cores), evs(p.evs)
  98 {
  99     for (int i = 0; i < p.cores.size(); i++)
 100         p.cores[i]->setCluster(this, i);
 101
 102     sc_core::sc_attr_base *base;
 103
 104     base = evs->get_attribute(Iris::Gem5CpuClusterAttributeName);
 105     auto *gem5_cluster_attr =
 106         dynamic_cast<sc_core::sc_attribute<CortexR52Cluster *> *>(base);
 107     panic_if(base && !gem5_cluster_attr,
 108              "The EVS gem5 CPU cluster attribute was not of type "
 109              "sc_attribute<FastModel::CortexR52Cluster *>.");
 110     if (gem5_cluster_attr)
 111         gem5_cluster_attr->value = this;
 112
 113     set_evs_param("core.CLUSTER_ID", params().CLUSTER_ID);
 114     set_evs_param("core.DBGROMADDR", params().DBGROMADDR);
 115     set_evs_param("core.DBGROMADDRV", params().DBGROMADDRV);
 116     set_evs_param("core.PERIPHBASE", params().PERIPHBASE);
 117     set_evs_param("core.cluster_utid", params().cluster_utid);
 118     set_evs_param("core.cpi_div", params().cpi_div);
 119     set_evs_param("core.cpi_mul", params().cpi_mul);
 120     set_evs_param("core.dcache-prefetch_enabled",
 121             params().dcache_prefetch_enabled);
 122     set_evs_param("core.dcache-read_access_latency",
 123             params().dcache_read_access_latency);
 124     set_evs_param("core.dcache-state_modelled",
 125             params().dcache_state_modelled);
 126     set_evs_param("core.dcache-write_access_latency",
 127             params().dcache_write_access_latency);
 128     set_evs_param("core.flash_protection_enable_at_reset",
 129             params().flash_protection_enable_at_reset);
 130     set_evs_param("core.has_flash_protection", params().has_flash_protection);
 131     set_evs_param("core.icache-prefetch_enabled",
 132             params().icache_prefetch_enabled);
 133     set_evs_param("core.icache-read_access_latency",
 134             params().icache_read_access_latency);
 135     set_evs_param("core.icache-state_modelled",
 136             params().icache_state_modelled);
 137     set_evs_param("core.memory.ext_slave_base",
 138             params().memory_ext_slave_base);
 139     set_evs_param("core.memory.flash_base", params().memory_flash_base);
 140     set_evs_param("core.memory.flash_size", params().memory_flash_size);
 141     // Use uint32_t, since the model doesn't like setting these as uint8_t.
 142     set_evs_param<uint32_t>("core.num_protection_regions_s1",
 143             params().num_protection_regions_s1);
 144     set_evs_param<uint32_t>("core.num_protection_regions_s2",
 145             params().num_protection_regions_s2);
 146     set_evs_param("core.num_spi", params().num_spi);
 147     set_evs_param("core.ram_protection_enable_at_reset",
 148             params().ram_protection_enable_at_reset);
 149     set_evs_param("core.has_export_m_port", params().has_export_m_port);
 150 }
 151
 152 Port &
 153 CortexR52Cluster::getPort(const std::string &if_name, PortID idx)
 154 {
 155     if (if_name == "spi") {
 156         return evs->gem5_getPort(if_name, idx);
 157     } else {
 158         return SimObject::getPort(if_name, idx);
 159     }
 160 }
 161
 162 } // namespace FastModel
 163
 164 FastModel::CortexR52 *
 165 FastModelCortexR52Params::create() const
 166 {
 167     return new FastModel::CortexR52(*this);
 168 }
 169
 170 FastModel::CortexR52Cluster *
 171 FastModelCortexR52ClusterParams::create() const
 172 {
 173     return new FastModel::CortexR52Cluster(*this);
 174 }