src/arch/arm/fastmodel/iris/interrupts.cc

   1 /*
   2  * Copyright 2019 Google Inc.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions are
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   7  * notice, this list of conditions and the following disclaimer;
   8  * redistributions in binary form must reproduce the above copyright
   9  * notice, this list of conditions and the following disclaimer in the
  10  * documentation and/or other materials provided with the distribution;
  11  * neither the name of the copyright holders nor the names of its
  12  * contributors may be used to endorse or promote products derived from
  13  * this software without specific prior written permission.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "arch/arm/fastmodel/iris/interrupts.hh"
  29
  30 #include "arch/arm/fastmodel/iris/thread_context.hh"
  31 #include "arch/arm/interrupts.hh"
  32 #include "arch/arm/miscregs.hh"
  33 #include "arch/arm/miscregs_types.hh"
  34 #include "arch/arm/types.hh"
  35 #include "params/IrisInterrupts.hh"
  36
  37 void
  38 Iris::Interrupts::serialize(CheckpointOut &cp) const
  39 {
  40     using namespace ArmISA;
  41
  42     CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
  43     CPSR orig_cpsr = cpsr;
  44     SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
  45     SCR orig_scr = scr;
  46     HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
  47     HCR orig_hcr = hcr;
  48
  49     // Set up state so we can get either physical or virtual interrupt bits.
  50     cpsr.mode = 0;
  51     cpsr.width = 0;
  52     cpsr.el = EL1;
  53     tc->setMiscReg(MISCREG_CPSR, cpsr);
  54     scr.eel2 = 1;
  55     tc->setMiscReg(MISCREG_SCR, scr);
  56
  57     // Get the virtual bits.
  58     hcr.imo = 1;
  59     hcr.fmo = 1;
  60     hcr.amo = 1;
  61     tc->setMiscReg(MISCREG_HCR_EL2, hcr);
  62
  63     RegVal isr_el1 = tc->readMiscRegNoEffect(MISCREG_ISR_EL1);
  64     // There is also a virtual abort, but it's not used by gem5.
  65     bool virt_irq = bits(7, isr_el1);
  66     bool virt_fiq = bits(6, isr_el1);
  67
  68     // Get the physical bits.
  69     hcr.imo = 0;
  70     hcr.fmo = 0;
  71     hcr.amo = 0;
  72     tc->setMiscReg(MISCREG_HCR_EL2, hcr);
  73
  74     isr_el1 = tc->readMiscRegNoEffect(MISCREG_ISR_EL1);
  75     bool phys_abort = bits(8, isr_el1);
  76     bool phys_irq = bits(7, isr_el1);
  77     bool phys_fiq = bits(6, isr_el1);
  78
  79     tc->setMiscReg(MISCREG_CPSR, orig_cpsr);
  80     tc->setMiscReg(MISCREG_SCR_EL3, orig_scr);
  81     tc->setMiscReg(MISCREG_HCR_EL2, orig_hcr);
  82
  83     bool interrupts[ArmISA::NumInterruptTypes];
  84     uint64_t intStatus = 0;
  85
  86     for (bool &i: interrupts)
  87         i = false;
  88
  89     interrupts[ArmISA::INT_ABT] = phys_abort;
  90     interrupts[ArmISA::INT_IRQ] = phys_irq;
  91     interrupts[ArmISA::INT_FIQ] = phys_fiq;
  92     interrupts[ArmISA::INT_SEV] = tc->readMiscReg(MISCREG_SEV_MAILBOX);
  93     interrupts[ArmISA::INT_VIRT_IRQ] = virt_irq;
  94     interrupts[ArmISA::INT_VIRT_FIQ] = virt_fiq;
  95
  96     for (int i = 0; i < NumInterruptTypes; i++) {
  97         if (interrupts[i])
  98             intStatus |= (0x1ULL << i);
  99     }
 100
 101     SERIALIZE_ARRAY(interrupts, NumInterruptTypes);
 102     SERIALIZE_SCALAR(intStatus);
 103 }
 104
 105 void
 106 Iris::Interrupts::unserialize(CheckpointIn &cp)
 107 {
 108 }
 109
 110 Iris::Interrupts *
 111 IrisInterruptsParams::create() const
 112 {
 113     return new Iris::Interrupts(*this);
 114 }