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28 #include "arch/arm/fastmodel/iris/interrupts.hh"
30 #include "arch/arm/fastmodel/iris/thread_context.hh"
31 #include "arch/arm/interrupts.hh"
32 #include "arch/arm/miscregs.hh"
33 #include "arch/arm/miscregs_types.hh"
34 #include "arch/arm/types.hh"
35 #include "params/IrisInterrupts.hh"
38 Iris::Interrupts::serialize(CheckpointOut
&cp
) const
40 using namespace ArmISA
;
42 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
43 CPSR orig_cpsr
= cpsr
;
44 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
46 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR_EL2
);
49 // Set up state so we can get either physical or virtual interrupt bits.
53 tc
->setMiscReg(MISCREG_CPSR
, cpsr
);
55 tc
->setMiscReg(MISCREG_SCR
, scr
);
57 // Get the virtual bits.
61 tc
->setMiscReg(MISCREG_HCR_EL2
, hcr
);
63 RegVal isr_el1
= tc
->readMiscRegNoEffect(MISCREG_ISR_EL1
);
64 // There is also a virtual abort, but it's not used by gem5.
65 bool virt_irq
= bits(7, isr_el1
);
66 bool virt_fiq
= bits(6, isr_el1
);
68 // Get the physical bits.
72 tc
->setMiscReg(MISCREG_HCR_EL2
, hcr
);
74 isr_el1
= tc
->readMiscRegNoEffect(MISCREG_ISR_EL1
);
75 bool phys_abort
= bits(8, isr_el1
);
76 bool phys_irq
= bits(7, isr_el1
);
77 bool phys_fiq
= bits(6, isr_el1
);
79 tc
->setMiscReg(MISCREG_CPSR
, orig_cpsr
);
80 tc
->setMiscReg(MISCREG_SCR_EL3
, orig_scr
);
81 tc
->setMiscReg(MISCREG_HCR_EL2
, orig_hcr
);
83 bool interrupts
[ArmISA::NumInterruptTypes
];
84 uint64_t intStatus
= 0;
86 for (bool &i
: interrupts
)
89 interrupts
[ArmISA::INT_ABT
] = phys_abort
;
90 interrupts
[ArmISA::INT_IRQ
] = phys_irq
;
91 interrupts
[ArmISA::INT_FIQ
] = phys_fiq
;
92 interrupts
[ArmISA::INT_SEV
] = tc
->readMiscReg(MISCREG_SEV_MAILBOX
);
93 interrupts
[ArmISA::INT_VIRT_IRQ
] = virt_irq
;
94 interrupts
[ArmISA::INT_VIRT_FIQ
] = virt_fiq
;
96 for (int i
= 0; i
< NumInterruptTypes
; i
++) {
98 intStatus
|= (0x1ULL
<< i
);
101 SERIALIZE_ARRAY(interrupts
, NumInterruptTypes
);
102 SERIALIZE_SCALAR(intStatus
);
106 Iris::Interrupts::unserialize(CheckpointIn
&cp
)