src/arch/arm/fastmodel/iris/thread_context.hh

   1 /*
   2  * Copyright 2019 Google, Inc.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions are
   6  * met: redistributions of source code must retain the above copyright
   7  * notice, this list of conditions and the following disclaimer;
   8  * redistributions in binary form must reproduce the above copyright
   9  * notice, this list of conditions and the following disclaimer in the
  10  * documentation and/or other materials provided with the distribution;
  11  * neither the name of the copyright holders nor the names of its
  12  * contributors may be used to endorse or promote products derived from
  13  * this software without specific prior written permission.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  * Authors: Gabe Black
  28  */
  29
  30 #ifndef __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__
  31 #define __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__
  32
  33 #include <list>
  34 #include <map>
  35 #include <memory>
  36
  37 #include "cpu/base.hh"
  38 #include "cpu/thread_context.hh"
  39 #include "iris/IrisInstance.h"
  40 #include "iris/detail/IrisErrorCode.h"
  41 #include "iris/detail/IrisObjects.h"
  42 #include "sim/system.hh"
  43
  44 namespace Iris
  45 {
  46
  47 // This class is the base for ThreadContexts which read and write state using
  48 // the Iris API.
  49 class ThreadContext : public ::ThreadContext
  50 {
  51   public:
  52     typedef std::map<std::string, iris::ResourceInfo> ResourceMap;
  53
  54     typedef std::vector<iris::ResourceId> ResourceIds;
  55     typedef std::map<int, std::string> IdxNameMap;
  56
  57   protected:
  58     ::BaseCPU *_cpu;
  59     int _threadId;
  60     ContextID _contextId;
  61     System *_system;
  62     ::BaseTLB *_dtb;
  63     ::BaseTLB *_itb;
  64
  65     std::string _irisPath;
  66     iris::InstanceId _instId = iris::IRIS_UINT64_MAX;
  67
  68     // Temporary holding places for the vector reg accessors to return.
  69     // These are not updated live, only when requested.
  70     mutable std::vector<ArmISA::VecRegContainer> vecRegs;
  71     mutable std::vector<ArmISA::VecPredRegContainer> vecPredRegs;
  72
  73     Status _status = Active;
  74
  75     virtual void initFromIrisInstance(const ResourceMap &resources);
  76
  77     iris::ResourceId extractResourceId(
  78             const ResourceMap &resources, const std::string &name);
  79     void extractResourceMap(ResourceIds &ids,
  80             const ResourceMap &resources, const IdxNameMap &idx_names);
  81
  82
  83     ResourceIds miscRegIds;
  84     ResourceIds intReg32Ids;
  85     ResourceIds intReg64Ids;
  86
  87     iris::ResourceId pcRscId = iris::IRIS_UINT64_MAX;
  88     iris::ResourceId icountRscId;
  89
  90     ResourceIds vecRegIds;
  91     ResourceIds vecPredRegIds;
  92
  93     std::vector<iris::MemorySpaceInfo> memorySpaces;
  94     std::vector<iris::MemorySupportedAddressTranslationResult> translations;
  95
  96     std::unique_ptr<PortProxy> virtProxy = nullptr;
  97     std::unique_ptr<PortProxy> physProxy = nullptr;
  98
  99
 100     // A queue to keep track of instruction count based events.
 101     EventQueue comInstEventQueue;
 102     // A helper function to maintain the IRIS step count. This makes sure the
 103     // step count is correct even after IRIS resets it for us, and also handles
 104     // events which are supposed to happen at the current instruction count.
 105     void maintainStepping();
 106
 107
 108     using BpId = uint64_t;
 109     struct BpInfo
 110     {
 111         Addr pc;
 112         BpId id;
 113         std::list<PCEvent *> events;
 114
 115         BpInfo(Addr _pc) : pc(_pc), id(iris::IRIS_UINT64_MAX) {}
 116
 117         bool empty() const { return events.empty(); }
 118         bool validId() const { return id != iris::IRIS_UINT64_MAX; }
 119         void clearId() { id = iris::IRIS_UINT64_MAX; }
 120     };
 121
 122     using BpInfoPtr = std::unique_ptr<BpInfo>;
 123     using BpInfoMap = std::map<Addr, BpInfoPtr>;
 124     using BpInfoIt = BpInfoMap::iterator;
 125
 126     BpInfoMap bps;
 127
 128     BpInfoIt getOrAllocBp(Addr pc);
 129
 130     void installBp(BpInfoIt it);
 131     void uninstallBp(BpInfoIt it);
 132     void delBp(BpInfoIt it);
 133
 134     virtual iris::MemorySpaceId getBpSpaceId(Addr pc) const = 0;
 135
 136
 137     iris::IrisErrorCode instanceRegistryChanged(
 138             uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
 139             uint64_t sInstId, bool syncEc, std::string &error_message_out);
 140     iris::IrisErrorCode phaseInitLeave(
 141             uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
 142             uint64_t sInstId, bool syncEc, std::string &error_message_out);
 143     iris::IrisErrorCode simulationTimeEvent(
 144             uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
 145             uint64_t sInstId, bool syncEc, std::string &error_message_out);
 146     iris::IrisErrorCode breakpointHit(
 147             uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
 148             uint64_t sInstId, bool syncEc, std::string &error_message_out);
 149
 150     iris::EventStreamId regEventStreamId;
 151     iris::EventStreamId initEventStreamId;
 152     iris::EventStreamId timeEventStreamId;
 153     iris::EventStreamId breakpointEventStreamId;
 154
 155     mutable iris::IrisInstance client;
 156     iris::IrisCppAdapter &call() const { return client.irisCall(); }
 157     iris::IrisCppAdapter &noThrow() const { return client.irisCallNoThrow(); }
 158
 159     bool translateAddress(Addr &paddr, iris::MemorySpaceId p_space,
 160                           Addr vaddr, iris::MemorySpaceId v_space);
 161
 162   public:
 163     ThreadContext(::BaseCPU *cpu, int id, System *system,
 164                   ::BaseTLB *dtb, ::BaseTLB *itb,
 165                   iris::IrisConnectionInterface *iris_if,
 166                   const std::string &iris_path);
 167     virtual ~ThreadContext();
 168
 169     virtual bool translateAddress(Addr &paddr, Addr vaddr) = 0;
 170
 171     bool schedule(PCEvent *e) override;
 172     bool remove(PCEvent *e) override;
 173
 174     void scheduleInstCountEvent(Event *event, Tick count) override;
 175     void descheduleInstCountEvent(Event *event) override;
 176     Tick getCurrentInstCount() override;
 177
 178     ::BaseCPU *getCpuPtr() override { return _cpu; }
 179     int cpuId() const override { return _cpu->cpuId(); }
 180     uint32_t socketId() const override { return _cpu->socketId(); }
 181
 182     int threadId() const override { return _threadId; }
 183     void setThreadId(int id) override { _threadId = id; }
 184
 185     int contextId() const override { return _contextId; }
 186     void setContextId(int id) override { _contextId = id; }
 187
 188     BaseTLB *
 189     getITBPtr() override
 190     {
 191         return _itb;
 192     }
 193     BaseTLB *
 194     getDTBPtr() override
 195     {
 196         return _dtb;
 197     }
 198     CheckerCPU *
 199     getCheckerCpuPtr() override
 200     {
 201         panic("%s not implemented.", __FUNCTION__);
 202     }
 203     ArmISA::Decoder *
 204     getDecoderPtr() override
 205     {
 206         panic("%s not implemented.", __FUNCTION__);
 207     }
 208
 209     System *getSystemPtr() override { return _cpu->system; }
 210
 211     ArmISA::ISA *
 212     getIsaPtr() override
 213     {
 214         panic("%s not implemented.", __FUNCTION__);
 215     }
 216
 217     Kernel::Statistics *
 218     getKernelStats() override
 219     {
 220         panic("%s not implemented.", __FUNCTION__);
 221     }
 222
 223     PortProxy &getPhysProxy() override { return *physProxy; }
 224     PortProxy &getVirtProxy() override { return *virtProxy; }
 225     void initMemProxies(::ThreadContext *tc) override;
 226
 227     Process *
 228     getProcessPtr() override
 229     {
 230         panic("%s not implemented.", __FUNCTION__);
 231     }
 232     void
 233     setProcessPtr(Process *p) override
 234     {
 235         panic("%s not implemented.", __FUNCTION__);
 236     }
 237
 238     Status status() const override;
 239     void setStatus(Status new_status) override;
 240     void activate() override { setStatus(Active); }
 241     void suspend() override { setStatus(Suspended); }
 242     void halt() override { setStatus(Halted); }
 243
 244     void
 245     dumpFuncProfile() override
 246     {
 247         panic("%s not implemented.", __FUNCTION__);
 248     }
 249
 250     void
 251     takeOverFrom(::ThreadContext *old_context) override
 252     {
 253         panic("%s not implemented.", __FUNCTION__);
 254     }
 255
 256     void regStats(const std::string &name) override {}
 257
 258     EndQuiesceEvent *
 259     getQuiesceEvent() override
 260     {
 261         panic("%s not implemented.", __FUNCTION__);
 262     }
 263
 264     // Not necessarily the best location for these...
 265     // Having an extra function just to read these is obnoxious
 266     Tick
 267     readLastActivate() override
 268     {
 269         panic("%s not implemented.", __FUNCTION__);
 270     }
 271     Tick readLastSuspend() override
 272     {
 273         panic("%s not implemented.", __FUNCTION__);
 274     }
 275
 276     void
 277     profileClear() override
 278     {
 279         panic("%s not implemented.", __FUNCTION__);
 280     }
 281     void
 282     profileSample() override
 283     {
 284         panic("%s not implemented.", __FUNCTION__);
 285     }
 286
 287     void
 288     copyArchRegs(::ThreadContext *tc) override
 289     {
 290         panic("%s not implemented.", __FUNCTION__);
 291     }
 292
 293     void
 294     clearArchRegs() override
 295     {
 296         panic("%s not implemented.", __FUNCTION__);
 297     }
 298
 299     //
 300     // New accessors for new decoder.
 301     //
 302     RegVal readIntReg(RegIndex reg_idx) const override;
 303
 304     RegVal
 305     readFloatReg(RegIndex reg_idx) const override
 306     {
 307         panic("%s not implemented.", __FUNCTION__);
 308     }
 309
 310     const VecRegContainer &readVecReg(const RegId &reg) const override;
 311     VecRegContainer &
 312     getWritableVecReg(const RegId &reg) override
 313     {
 314         panic("%s not implemented.", __FUNCTION__);
 315     }
 316
 317     /** Vector Register Lane Interfaces. */
 318     /** @{ */
 319     /** Reads source vector 8bit operand. */
 320     ConstVecLane8
 321     readVec8BitLaneReg(const RegId &reg) const override
 322     {
 323         panic("%s not implemented.", __FUNCTION__);
 324     }
 325
 326     /** Reads source vector 16bit operand. */
 327     ConstVecLane16
 328     readVec16BitLaneReg(const RegId &reg) const override
 329     {
 330         panic("%s not implemented.", __FUNCTION__);
 331     }
 332
 333     /** Reads source vector 32bit operand. */
 334     ConstVecLane32
 335     readVec32BitLaneReg(const RegId &reg) const override
 336     {
 337         panic("%s not implemented.", __FUNCTION__);
 338     }
 339
 340     /** Reads source vector 64bit operand. */
 341     ConstVecLane64
 342     readVec64BitLaneReg(const RegId &reg) const override
 343     {
 344         panic("%s not implemented.", __FUNCTION__);
 345     }
 346
 347     /** Write a lane of the destination vector register. */
 348     void
 349     setVecLane(const RegId &reg, const LaneData<LaneSize::Byte> &val) override
 350     {
 351         panic("%s not implemented.", __FUNCTION__);
 352     }
 353     void
 354     setVecLane(const RegId &reg,
 355                const LaneData<LaneSize::TwoByte> &val) override
 356     {
 357         panic("%s not implemented.", __FUNCTION__);
 358     }
 359     void
 360     setVecLane(const RegId &reg,
 361                const LaneData<LaneSize::FourByte> &val) override
 362     {
 363         panic("%s not implemented.", __FUNCTION__);
 364     }
 365     void
 366     setVecLane(const RegId &reg,
 367                const LaneData<LaneSize::EightByte> &val) override
 368     {
 369         panic("%s not implemented.", __FUNCTION__);
 370     }
 371     /** @} */
 372
 373     const VecElem &
 374     readVecElem(const RegId &reg) const override
 375     {
 376         panic("%s not implemented.", __FUNCTION__);
 377     }
 378
 379     const VecPredRegContainer &readVecPredReg(const RegId &reg) const override;
 380     VecPredRegContainer &
 381     getWritableVecPredReg(const RegId &reg) override
 382     {
 383         panic("%s not implemented.", __FUNCTION__);
 384     }
 385
 386     RegVal
 387     readCCReg(RegIndex reg_idx) const override
 388     {
 389         panic("%s not implemented.", __FUNCTION__);
 390     }
 391
 392     void setIntReg(RegIndex reg_idx, RegVal val) override;
 393
 394     void
 395     setFloatReg(RegIndex reg_idx, RegVal val) override
 396     {
 397         panic("%s not implemented.", __FUNCTION__);
 398     }
 399
 400     void
 401     setVecReg(const RegId &reg, const VecRegContainer &val) override
 402     {
 403         panic("%s not implemented.", __FUNCTION__);
 404     }
 405
 406     void
 407     setVecElem(const RegId& reg, const VecElem& val) override
 408     {
 409         panic("%s not implemented.", __FUNCTION__);
 410     }
 411
 412     void
 413     setVecPredReg(const RegId &reg,
 414                   const VecPredRegContainer &val) override
 415     {
 416         panic("%s not implemented.", __FUNCTION__);
 417     }
 418
 419     void
 420     setCCReg(RegIndex reg_idx, RegVal val) override
 421     {
 422         panic("%s not implemented.", __FUNCTION__);
 423     }
 424
 425     void pcStateNoRecord(const ArmISA::PCState &val) override { pcState(val); }
 426     MicroPC microPC() const override { return 0; }
 427
 428     ArmISA::PCState pcState() const override;
 429     void pcState(const ArmISA::PCState &val) override;
 430     Addr instAddr() const override;
 431     Addr nextInstAddr() const override;
 432
 433     RegVal readMiscRegNoEffect(RegIndex misc_reg) const override;
 434     RegVal
 435     readMiscReg(RegIndex misc_reg) override
 436     {
 437         return readMiscRegNoEffect(misc_reg);
 438     }
 439
 440     void setMiscRegNoEffect(RegIndex misc_reg, const RegVal val) override;
 441     void
 442     setMiscReg(RegIndex misc_reg, const RegVal val) override
 443     {
 444         setMiscRegNoEffect(misc_reg, val);
 445     }
 446
 447     RegId
 448     flattenRegId(const RegId& regId) const override
 449     {
 450         panic("%s not implemented.", __FUNCTION__);
 451     }
 452
 453     // Also not necessarily the best location for these two.  Hopefully will go
 454     // away once we decide upon where st cond failures goes.
 455     unsigned
 456     readStCondFailures() const override
 457     {
 458         panic("%s not implemented.", __FUNCTION__);
 459     }
 460
 461     void
 462     setStCondFailures(unsigned sc_failures) override
 463     {
 464         panic("%s not implemented.", __FUNCTION__);
 465     }
 466
 467     // Same with st cond failures.
 468     Counter
 469     readFuncExeInst() const override
 470     {
 471         panic("%s not implemented.", __FUNCTION__);
 472     }
 473
 474     void
 475     syscall(Fault *fault) override
 476     {
 477         panic("%s not implemented.", __FUNCTION__);
 478     }
 479
 480     /** @{ */
 481     /**
 482      * Flat register interfaces
 483      *
 484      * Some architectures have different registers visible in
 485      * different modes. Such architectures "flatten" a register (see
 486      * flattenRegId()) to map it into the
 487      * gem5 register file. This interface provides a flat interface to
 488      * the underlying register file, which allows for example
 489      * serialization code to access all registers.
 490      */
 491
 492     uint64_t
 493     readIntRegFlat(RegIndex idx) const override
 494     {
 495         panic("%s not implemented.", __FUNCTION__);
 496     }
 497     void
 498     setIntRegFlat(RegIndex idx, uint64_t val) override
 499     {
 500         panic("%s not implemented.", __FUNCTION__);
 501     }
 502
 503     RegVal
 504     readFloatRegFlat(RegIndex idx) const override
 505     {
 506         panic("%s not implemented.", __FUNCTION__);
 507     }
 508     void
 509     setFloatRegFlat(RegIndex idx, RegVal val) override
 510     {
 511         panic("%s not implemented.", __FUNCTION__);
 512     }
 513
 514     const VecRegContainer &readVecRegFlat(RegIndex idx) const override;
 515     VecRegContainer &
 516     getWritableVecRegFlat(RegIndex idx) override
 517     {
 518         panic("%s not implemented.", __FUNCTION__);
 519     }
 520     void
 521     setVecRegFlat(RegIndex idx, const VecRegContainer &val) override
 522     {
 523         panic("%s not implemented.", __FUNCTION__);
 524     }
 525
 526     const VecElem&
 527     readVecElemFlat(RegIndex idx, const ElemIndex& elemIdx) const override
 528     {
 529         panic("%s not implemented.", __FUNCTION__);
 530     }
 531     void
 532     setVecElemFlat(RegIndex idx, const ElemIndex &elemIdx,
 533                    const VecElem &val) override
 534     {
 535         panic("%s not implemented.", __FUNCTION__);
 536     }
 537
 538     const VecPredRegContainer &readVecPredRegFlat(RegIndex idx) const override;
 539     VecPredRegContainer &
 540     getWritableVecPredRegFlat(RegIndex idx) override
 541     {
 542         panic("%s not implemented.", __FUNCTION__);
 543     }
 544     void
 545     setVecPredRegFlat(RegIndex idx, const VecPredRegContainer &val) override
 546     {
 547         panic("%s not implemented.", __FUNCTION__);
 548     }
 549
 550     RegVal
 551     readCCRegFlat(RegIndex idx) const override
 552     {
 553         panic("%s not implemented.", __FUNCTION__);
 554     }
 555     void
 556     setCCRegFlat(RegIndex idx, RegVal val) override
 557     {
 558         panic("%s not implemented.", __FUNCTION__);
 559     }
 560     /** @} */
 561
 562 };
 563
 564 } // namespace Iris
 565
 566 #endif // __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__