src/arch/arm/fastmodel/iris/thread_context.hh

   1 /*
   2  * Copyright 2019 Google, Inc.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions are
   6  * met: redistributions of source code must retain the above copyright
   7  * notice, this list of conditions and the following disclaimer;
   8  * redistributions in binary form must reproduce the above copyright
   9  * notice, this list of conditions and the following disclaimer in the
  10  * documentation and/or other materials provided with the distribution;
  11  * neither the name of the copyright holders nor the names of its
  12  * contributors may be used to endorse or promote products derived from
  13  * this software without specific prior written permission.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  * Authors: Gabe Black
  28  */
  29
  30 #ifndef __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__
  31 #define __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__
  32
  33 #include "cpu/base.hh"
  34 #include "cpu/thread_context.hh"
  35 #include "iris/IrisInstance.h"
  36 #include "iris/detail/IrisErrorCode.h"
  37 #include "iris/detail/IrisObjects.h"
  38 #include "sim/system.hh"
  39
  40 namespace Iris
  41 {
  42
  43 // This class is the base for ThreadContexts which read and write state using
  44 // the Iris API.
  45 class ThreadContext : public ::ThreadContext
  46 {
  47   public:
  48     typedef std::map<std::string, iris::ResourceInfo> ResourceMap;
  49
  50     typedef std::vector<iris::ResourceId> ResourceIds;
  51     typedef std::map<int, std::string> IdxNameMap;
  52
  53   protected:
  54     ::BaseCPU *_cpu;
  55     int _threadId;
  56     ContextID _contextId;
  57     System *_system;
  58
  59     std::string _irisPath;
  60     iris::InstanceId _instId;
  61
  62     Status _status;
  63
  64     virtual void initFromIrisInstance(const ResourceMap &resources);
  65
  66     iris::ResourceId extractResourceId(
  67             const ResourceMap &resources, const std::string &name);
  68     void extractResourceMap(ResourceIds &ids,
  69             const ResourceMap &resources, const IdxNameMap &idx_names);
  70
  71
  72     ResourceIds miscRegIds;
  73     ResourceIds intRegIds;
  74
  75
  76     iris::IrisErrorCode instanceRegistryChanged(
  77             uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
  78             uint64_t sInstId, bool syncEc, std::string &error_message_out);
  79     iris::IrisErrorCode phaseInitLeave(
  80             uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
  81             uint64_t sInstId, bool syncEc, std::string &error_message_out);
  82
  83     iris::EventStreamId regEventStreamId;
  84     iris::EventStreamId initEventStreamId;
  85
  86     mutable iris::IrisInstance client;
  87     iris::IrisCppAdapter &call() const { return client.irisCall(); }
  88     iris::IrisCppAdapter &noThrow() const { return client.irisCallNoThrow(); }
  89
  90   public:
  91     ThreadContext(::BaseCPU *cpu, int id, System *system,
  92                   iris::IrisConnectionInterface *iris_if,
  93                   const std::string &iris_path);
  94     virtual ~ThreadContext();
  95
  96     bool schedule(PCEvent *e) override { return false; }
  97     bool remove(PCEvent *e) override { return false; }
  98
  99     void scheduleInstCountEvent(Event *event, Tick count) override {}
 100     void descheduleInstCountEvent(Event *event) override {}
 101     Tick getCurrentInstCount() override;
 102
 103     ::BaseCPU *getCpuPtr() override { return _cpu; }
 104     int cpuId() const override { return _cpu->cpuId(); }
 105     uint32_t socketId() const override { return _cpu->socketId(); }
 106
 107     int threadId() const override { return _threadId; }
 108     void setThreadId(int id) override { _threadId = id; }
 109
 110     int contextId() const override { return _contextId; }
 111     void setContextId(int id) override { _contextId = id; }
 112
 113     BaseTLB *
 114     getITBPtr() override
 115     {
 116         panic("%s not implemented.", __FUNCTION__);
 117     }
 118     BaseTLB *
 119     getDTBPtr() override
 120     {
 121         panic("%s not implemented.", __FUNCTION__);
 122     }
 123     CheckerCPU *
 124     getCheckerCpuPtr() override
 125     {
 126         panic("%s not implemented.", __FUNCTION__);
 127     }
 128     TheISA::Decoder *
 129     getDecoderPtr() override
 130     {
 131         panic("%s not implemented.", __FUNCTION__);
 132     }
 133
 134     System *getSystemPtr() override { return _cpu->system; }
 135
 136     Kernel::Statistics *
 137     getKernelStats() override
 138     {
 139         panic("%s not implemented.", __FUNCTION__);
 140     }
 141     PortProxy &
 142     getPhysProxy() override
 143     {
 144         panic("%s not implemented.", __FUNCTION__);
 145     }
 146     PortProxy &
 147     getVirtProxy() override
 148     {
 149         panic("%s not implemented.", __FUNCTION__);
 150     }
 151     void
 152     initMemProxies(::ThreadContext *tc) override
 153     {
 154         panic("%s not implemented.", __FUNCTION__);
 155     }
 156     Process *
 157     getProcessPtr() override
 158     {
 159         panic("%s not implemented.", __FUNCTION__);
 160     }
 161     void
 162     setProcessPtr(Process *p) override
 163     {
 164         panic("%s not implemented.", __FUNCTION__);
 165     }
 166
 167     Status status() const override;
 168     void setStatus(Status new_status) override;
 169     void activate() override { setStatus(Active); }
 170     void suspend() override { setStatus(Suspended); }
 171     void halt() override { setStatus(Halted); }
 172
 173     void
 174     dumpFuncProfile() override
 175     {
 176         panic("%s not implemented.", __FUNCTION__);
 177     }
 178
 179     void
 180     takeOverFrom(::ThreadContext *old_context) override
 181     {
 182         panic("%s not implemented.", __FUNCTION__);
 183     }
 184
 185     void regStats(const std::string &name) override {}
 186
 187     EndQuiesceEvent *
 188     getQuiesceEvent() override
 189     {
 190         panic("%s not implemented.", __FUNCTION__);
 191     }
 192
 193     // Not necessarily the best location for these...
 194     // Having an extra function just to read these is obnoxious
 195     Tick
 196     readLastActivate() override
 197     {
 198         panic("%s not implemented.", __FUNCTION__);
 199     }
 200     Tick readLastSuspend() override
 201     {
 202         panic("%s not implemented.", __FUNCTION__);
 203     }
 204
 205     void
 206     profileClear() override
 207     {
 208         panic("%s not implemented.", __FUNCTION__);
 209     }
 210     void
 211     profileSample() override
 212     {
 213         panic("%s not implemented.", __FUNCTION__);
 214     }
 215
 216     void
 217     copyArchRegs(::ThreadContext *tc) override
 218     {
 219         panic("%s not implemented.", __FUNCTION__);
 220     }
 221
 222     void
 223     clearArchRegs() override
 224     {
 225         panic("%s not implemented.", __FUNCTION__);
 226     }
 227
 228     //
 229     // New accessors for new decoder.
 230     //
 231     RegVal readIntReg(RegIndex reg_idx) const override;
 232
 233     RegVal
 234     readFloatReg(RegIndex reg_idx) const override
 235     {
 236         panic("%s not implemented.", __FUNCTION__);
 237     }
 238
 239     const VecRegContainer &
 240     readVecReg(const RegId &reg) const override
 241     {
 242         panic("%s not implemented.", __FUNCTION__);
 243     }
 244     VecRegContainer &
 245     getWritableVecReg(const RegId &reg) override
 246     {
 247         panic("%s not implemented.", __FUNCTION__);
 248     }
 249
 250     /** Vector Register Lane Interfaces. */
 251     /** @{ */
 252     /** Reads source vector 8bit operand. */
 253     ConstVecLane8
 254     readVec8BitLaneReg(const RegId &reg) const override
 255     {
 256         panic("%s not implemented.", __FUNCTION__);
 257     }
 258
 259     /** Reads source vector 16bit operand. */
 260     ConstVecLane16
 261     readVec16BitLaneReg(const RegId &reg) const override
 262     {
 263         panic("%s not implemented.", __FUNCTION__);
 264     }
 265
 266     /** Reads source vector 32bit operand. */
 267     ConstVecLane32
 268     readVec32BitLaneReg(const RegId &reg) const override
 269     {
 270         panic("%s not implemented.", __FUNCTION__);
 271     }
 272
 273     /** Reads source vector 64bit operand. */
 274     ConstVecLane64
 275     readVec64BitLaneReg(const RegId &reg) const override
 276     {
 277         panic("%s not implemented.", __FUNCTION__);
 278     }
 279
 280     /** Write a lane of the destination vector register. */
 281     void
 282     setVecLane(const RegId &reg, const LaneData<LaneSize::Byte> &val) override
 283     {
 284         panic("%s not implemented.", __FUNCTION__);
 285     }
 286     void
 287     setVecLane(const RegId &reg,
 288                const LaneData<LaneSize::TwoByte> &val) override
 289     {
 290         panic("%s not implemented.", __FUNCTION__);
 291     }
 292     void
 293     setVecLane(const RegId &reg,
 294                const LaneData<LaneSize::FourByte> &val) override
 295     {
 296         panic("%s not implemented.", __FUNCTION__);
 297     }
 298     void
 299     setVecLane(const RegId &reg,
 300                const LaneData<LaneSize::EightByte> &val) override
 301     {
 302         panic("%s not implemented.", __FUNCTION__);
 303     }
 304     /** @} */
 305
 306     const VecElem &
 307     readVecElem(const RegId &reg) const override
 308     {
 309         panic("%s not implemented.", __FUNCTION__);
 310     }
 311
 312     const VecPredRegContainer &
 313     readVecPredReg(const RegId &reg) const override
 314     {
 315         panic("%s not implemented.", __FUNCTION__);
 316     }
 317     VecPredRegContainer &
 318     getWritableVecPredReg(const RegId &reg) override
 319     {
 320         panic("%s not implemented.", __FUNCTION__);
 321     }
 322
 323     RegVal
 324     readCCReg(RegIndex reg_idx) const override
 325     {
 326         panic("%s not implemented.", __FUNCTION__);
 327     }
 328
 329     void setIntReg(RegIndex reg_idx, RegVal val) override;
 330
 331     void
 332     setFloatReg(RegIndex reg_idx, RegVal val) override
 333     {
 334         panic("%s not implemented.", __FUNCTION__);
 335     }
 336
 337     void
 338     setVecReg(const RegId &reg, const VecRegContainer &val) override
 339     {
 340         panic("%s not implemented.", __FUNCTION__);
 341     }
 342
 343     void
 344     setVecElem(const RegId& reg, const VecElem& val) override
 345     {
 346         panic("%s not implemented.", __FUNCTION__);
 347     }
 348
 349     void
 350     setVecPredReg(const RegId &reg,
 351                   const VecPredRegContainer &val) override
 352     {
 353         panic("%s not implemented.", __FUNCTION__);
 354     }
 355
 356     void
 357     setCCReg(RegIndex reg_idx, RegVal val) override
 358     {
 359         panic("%s not implemented.", __FUNCTION__);
 360     }
 361
 362     void pcStateNoRecord(const TheISA::PCState &val) override { pcState(val); }
 363     MicroPC microPC() const override { return 0; }
 364
 365     RegVal readMiscRegNoEffect(RegIndex misc_reg) const override;
 366     RegVal
 367     readMiscReg(RegIndex misc_reg) override
 368     {
 369         return readMiscRegNoEffect(misc_reg);
 370     }
 371
 372     void setMiscRegNoEffect(RegIndex misc_reg, const RegVal val) override;
 373     void
 374     setMiscReg(RegIndex misc_reg, const RegVal val) override
 375     {
 376         setMiscRegNoEffect(misc_reg, val);
 377     }
 378
 379     RegId
 380     flattenRegId(const RegId& regId) const override
 381     {
 382         panic("%s not implemented.", __FUNCTION__);
 383     }
 384
 385     // Also not necessarily the best location for these two.  Hopefully will go
 386     // away once we decide upon where st cond failures goes.
 387     unsigned
 388     readStCondFailures() const override
 389     {
 390         panic("%s not implemented.", __FUNCTION__);
 391     }
 392
 393     void
 394     setStCondFailures(unsigned sc_failures) override
 395     {
 396         panic("%s not implemented.", __FUNCTION__);
 397     }
 398
 399     // Same with st cond failures.
 400     Counter
 401     readFuncExeInst() const override
 402     {
 403         panic("%s not implemented.", __FUNCTION__);
 404     }
 405
 406     void
 407     syscall(int64_t callnum, Fault *fault) override
 408     {
 409         panic("%s not implemented.", __FUNCTION__);
 410     }
 411
 412     /** @{ */
 413     /**
 414      * Flat register interfaces
 415      *
 416      * Some architectures have different registers visible in
 417      * different modes. Such architectures "flatten" a register (see
 418      * flattenRegId()) to map it into the
 419      * gem5 register file. This interface provides a flat interface to
 420      * the underlying register file, which allows for example
 421      * serialization code to access all registers.
 422      */
 423
 424     uint64_t
 425     readIntRegFlat(RegIndex idx) const override
 426     {
 427         panic("%s not implemented.", __FUNCTION__);
 428     }
 429     void
 430     setIntRegFlat(RegIndex idx, uint64_t val) override
 431     {
 432         panic("%s not implemented.", __FUNCTION__);
 433     }
 434
 435     RegVal
 436     readFloatRegFlat(RegIndex idx) const override
 437     {
 438         panic("%s not implemented.", __FUNCTION__);
 439     }
 440     void
 441     setFloatRegFlat(RegIndex idx, RegVal val) override
 442     {
 443         panic("%s not implemented.", __FUNCTION__);
 444     }
 445
 446     const VecRegContainer &
 447     readVecRegFlat(RegIndex idx) const override
 448     {
 449         panic("%s not implemented.", __FUNCTION__);
 450     }
 451     VecRegContainer &
 452     getWritableVecRegFlat(RegIndex idx) override
 453     {
 454         panic("%s not implemented.", __FUNCTION__);
 455     }
 456     void
 457     setVecRegFlat(RegIndex idx, const VecRegContainer &val) override
 458     {
 459         panic("%s not implemented.", __FUNCTION__);
 460     }
 461
 462     const VecElem&
 463     readVecElemFlat(RegIndex idx, const ElemIndex& elemIdx) const override
 464     {
 465         panic("%s not implemented.", __FUNCTION__);
 466     }
 467     void
 468     setVecElemFlat(RegIndex idx, const ElemIndex &elemIdx,
 469                    const VecElem &val) override
 470     {
 471         panic("%s not implemented.", __FUNCTION__);
 472     }
 473
 474     const VecPredRegContainer &
 475     readVecPredRegFlat(RegIndex idx) const override
 476     {
 477         panic("%s not implemented.", __FUNCTION__);
 478     }
 479     VecPredRegContainer &
 480     getWritableVecPredRegFlat(RegIndex idx) override
 481     {
 482         panic("%s not implemented.", __FUNCTION__);
 483     }
 484     void
 485     setVecPredRegFlat(RegIndex idx, const VecPredRegContainer &val) override
 486     {
 487         panic("%s not implemented.", __FUNCTION__);
 488     }
 489
 490     RegVal
 491     readCCRegFlat(RegIndex idx) const override
 492     {
 493         panic("%s not implemented.", __FUNCTION__);
 494     }
 495     void
 496     setCCRegFlat(RegIndex idx, RegVal val) override
 497     {
 498         panic("%s not implemented.", __FUNCTION__);
 499     }
 500     /** @} */
 501
 502 };
 503
 504 } // namespace Iris
 505
 506 #endif // __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__