01d43f3385842b2a49b7a770b70a0afd5422ead3
2 * Copyright (c) 2010 ARM Limited
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14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
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45 #include "arch/arm/faults.hh"
46 #include "cpu/thread_context.hh"
47 #include "cpu/base.hh"
48 #include "base/trace.hh"
53 template<> ArmFault::FaultVals ArmFaultVals
<Reset
>::vals
=
54 {"reset", 0x00, MODE_SVC
, 0, 0, true, true};
56 template<> ArmFault::FaultVals ArmFaultVals
<UndefinedInstruction
>::vals
=
57 {"Undefined Instruction", 0x04, MODE_UNDEFINED
, 4 ,2, false, false} ;
59 template<> ArmFault::FaultVals ArmFaultVals
<SupervisorCall
>::vals
=
60 {"Supervisor Call", 0x08, MODE_SVC
, 4, 2, false, false};
62 template<> ArmFault::FaultVals ArmFaultVals
<PrefetchAbort
>::vals
=
63 {"Prefetch Abort", 0x0C, MODE_ABORT
, 4, 4, true, false};
65 template<> ArmFault::FaultVals ArmFaultVals
<DataAbort
>::vals
=
66 {"Data Abort", 0x10, MODE_ABORT
, 8, 8, true, false};
68 template<> ArmFault::FaultVals ArmFaultVals
<Interrupt
>::vals
=
69 {"IRQ", 0x18, MODE_IRQ
, 4, 4, true, false};
71 template<> ArmFault::FaultVals ArmFaultVals
<FastInterrupt
>::vals
=
72 {"FIQ", 0x1C, MODE_FIQ
, 4, 4, true, true};
74 template<> ArmFault::FaultVals ArmFaultVals
<FlushPipe
>::vals
=
75 {"Pipe Flush", 0x00, MODE_SVC
, 0, 0, true, true}; // some dummy values
77 template<> ArmFault::FaultVals ArmFaultVals
<ReExec
>::vals
=
78 {"ReExec Flush", 0x00, MODE_SVC
, 0, 0, true, true}; // some dummy values
81 ArmFault::getVector(ThreadContext
*tc
)
85 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR
);
87 // panic if SCTLR.VE because I have no idea what to do with vectored
93 return offset() + HighVecs
;
100 ArmFault::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
103 FaultBase::invoke(tc
);
106 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR
);
107 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
108 CPSR saved_cpsr
= tc
->readMiscReg(MISCREG_CPSR
) |
109 tc
->readIntReg(INTREG_CONDCODES
);
110 Addr curPc M5_VAR_USED
= tc
->pcState().pc();
111 ITSTATE it
= tc
->pcState().itstate();
112 saved_cpsr
.it2
= it
.top6
;
113 saved_cpsr
.it1
= it
.bottom2
;
115 cpsr
.mode
= nextMode();
116 cpsr
.it1
= cpsr
.it2
= 0;
120 cpsr
.a
= cpsr
.a
| abortDisable();
121 cpsr
.f
= cpsr
.f
| fiqDisable();
124 tc
->setMiscReg(MISCREG_CPSR
, cpsr
);
125 tc
->setIntReg(INTREG_LR
, curPc
+
126 (saved_cpsr
.t
? thumbPcOffset() : armPcOffset()));
128 switch (nextMode()) {
130 tc
->setMiscReg(MISCREG_SPSR_FIQ
, saved_cpsr
);
133 tc
->setMiscReg(MISCREG_SPSR_IRQ
, saved_cpsr
);
136 tc
->setMiscReg(MISCREG_SPSR_SVC
, saved_cpsr
);
139 tc
->setMiscReg(MISCREG_SPSR_UND
, saved_cpsr
);
142 tc
->setMiscReg(MISCREG_SPSR_ABT
, saved_cpsr
);
145 panic("unknown Mode\n");
148 Addr newPc
= getVector(tc
);
149 DPRINTF(Faults
, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
150 name(), cpsr
, curPc
, tc
->readIntReg(INTREG_LR
), newPc
);
153 pc
.nextThumb(pc
.thumb());
155 pc
.nextJazelle(pc
.jazelle());
160 Reset::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
162 tc
->getCpuPtr()->clearInterrupts();
164 ArmFault::invoke(tc
, inst
);
170 UndefinedInstruction::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
172 // If the mnemonic isn't defined this has to be an unknown instruction.
173 assert(unknown
|| mnemonic
!= NULL
);
175 panic("Attempted to execute disabled instruction "
176 "'%s' (inst 0x%08x)", mnemonic
, machInst
);
177 } else if (unknown
) {
178 panic("Attempted to execute unknown instruction (inst 0x%08x)",
181 panic("Attempted to execute unimplemented instruction "
182 "'%s' (inst 0x%08x)", mnemonic
, machInst
);
187 SupervisorCall::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
189 // As of now, there isn't a 32 bit thumb version of this instruction.
190 assert(!machInst
.bigThumb
);
192 callNum
= tc
->readIntReg(INTREG_R7
);
193 tc
->syscall(callNum
);
195 // Advance the PC since that won't happen automatically.
196 PCState pc
= tc
->pcState();
202 #endif // FULL_SYSTEM
206 AbortFault
<T
>::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
208 ArmFaultVals
<T
>::invoke(tc
, inst
);
210 fsr
.fsLow
= bits(status
, 3, 0);
211 fsr
.fsHigh
= bits(status
, 4);
213 fsr
.wnr
= (write
? 1 : 0);
215 tc
->setMiscReg(T::FsrIndex
, fsr
);
216 tc
->setMiscReg(T::FarIndex
, faultAddr
);
220 FlushPipe::invoke(ThreadContext
*tc
, StaticInstPtr inst
) {
221 DPRINTF(Faults
, "Invoking FlushPipe Fault\n");
223 // Set the PC to the next instruction of the faulting instruction.
224 // Net effect is simply squashing all instructions behind and
225 // start refetching from the next instruction.
226 PCState pc
= tc
->pcState();
233 ReExec::invoke(ThreadContext
*tc
, StaticInstPtr inst
) {
234 DPRINTF(Faults
, "Invoking ReExec Fault\n");
236 // Set the PC to then the faulting instruction.
237 // Net effect is simply squashing all instructions including this
238 // instruction and refetching/rexecuting current instruction
239 PCState pc
= tc
->pcState();
243 template void AbortFault
<PrefetchAbort
>::invoke(ThreadContext
*tc
,
245 template void AbortFault
<DataAbort
>::invoke(ThreadContext
*tc
,
248 // return via SUBS pc, lr, xxx; rfe, movs, ldm
250 } // namespace ArmISA