2 * Copyright (c) 2010, 2012-2014, 2016-2017 ARM Limited
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15 * Copyright (c) 2007-2008 The Florida State University
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47 #include "arch/arm/faults.hh"
49 #include "arch/arm/insts/static_inst.hh"
50 #include "arch/arm/system.hh"
51 #include "arch/arm/utility.hh"
52 #include "base/compiler.hh"
53 #include "base/trace.hh"
54 #include "cpu/base.hh"
55 #include "cpu/thread_context.hh"
56 #include "debug/Faults.hh"
57 #include "sim/full_system.hh"
62 uint8_t ArmFault::shortDescFaultSources
[] = {
63 0x01, // AlignmentFault
64 0x04, // InstructionCacheMaintenance
65 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID)
66 0x0c, // SynchExtAbtOnTranslTableWalkL1
67 0x0e, // SynchExtAbtOnTranslTableWalkL2
68 0xff, // SynchExtAbtOnTranslTableWalkL3 (INVALID)
69 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID)
70 0x1c, // SynchPtyErrOnTranslTableWalkL1
71 0x1e, // SynchPtyErrOnTranslTableWalkL2
72 0xff, // SynchPtyErrOnTranslTableWalkL3 (INVALID)
73 0xff, // TranslationL0 (INVALID)
74 0x05, // TranslationL1
75 0x07, // TranslationL2
76 0xff, // TranslationL3 (INVALID)
77 0xff, // AccessFlagL0 (INVALID)
80 0xff, // AccessFlagL3 (INVALID)
81 0xff, // DomainL0 (INVALID)
84 0xff, // DomainL3 (INVALID)
85 0xff, // PermissionL0 (INVALID)
88 0xff, // PermissionL3 (INVALID)
90 0x08, // SynchronousExternalAbort
91 0x10, // TLBConflictAbort
92 0x19, // SynchPtyErrOnMemoryAccess
93 0x16, // AsynchronousExternalAbort
94 0x18, // AsynchPtyErrOnMemoryAccess
95 0xff, // AddressSizeL0 (INVALID)
96 0xff, // AddressSizeL1 (INVALID)
97 0xff, // AddressSizeL2 (INVALID)
98 0xff, // AddressSizeL3 (INVALID)
99 0x40, // PrefetchTLBMiss
100 0x80 // PrefetchUncacheable
103 static_assert(sizeof(ArmFault::shortDescFaultSources
) ==
104 ArmFault::NumFaultSources
,
105 "Invalid size of ArmFault::shortDescFaultSources[]");
107 uint8_t ArmFault::longDescFaultSources
[] = {
108 0x21, // AlignmentFault
109 0xff, // InstructionCacheMaintenance (INVALID)
110 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID)
111 0x15, // SynchExtAbtOnTranslTableWalkL1
112 0x16, // SynchExtAbtOnTranslTableWalkL2
113 0x17, // SynchExtAbtOnTranslTableWalkL3
114 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID)
115 0x1d, // SynchPtyErrOnTranslTableWalkL1
116 0x1e, // SynchPtyErrOnTranslTableWalkL2
117 0x1f, // SynchPtyErrOnTranslTableWalkL3
118 0xff, // TranslationL0 (INVALID)
119 0x05, // TranslationL1
120 0x06, // TranslationL2
121 0x07, // TranslationL3
122 0xff, // AccessFlagL0 (INVALID)
123 0x09, // AccessFlagL1
124 0x0a, // AccessFlagL2
125 0x0b, // AccessFlagL3
126 0xff, // DomainL0 (INVALID)
129 0xff, // DomainL3 (RESERVED)
130 0xff, // PermissionL0 (INVALID)
131 0x0d, // PermissionL1
132 0x0e, // PermissionL2
133 0x0f, // PermissionL3
135 0x10, // SynchronousExternalAbort
136 0x30, // TLBConflictAbort
137 0x18, // SynchPtyErrOnMemoryAccess
138 0x11, // AsynchronousExternalAbort
139 0x19, // AsynchPtyErrOnMemoryAccess
140 0xff, // AddressSizeL0 (INVALID)
141 0xff, // AddressSizeL1 (INVALID)
142 0xff, // AddressSizeL2 (INVALID)
143 0xff, // AddressSizeL3 (INVALID)
144 0x40, // PrefetchTLBMiss
145 0x80 // PrefetchUncacheable
148 static_assert(sizeof(ArmFault::longDescFaultSources
) ==
149 ArmFault::NumFaultSources
,
150 "Invalid size of ArmFault::longDescFaultSources[]");
152 uint8_t ArmFault::aarch64FaultSources
[] = {
153 0x21, // AlignmentFault
154 0xff, // InstructionCacheMaintenance (INVALID)
155 0x14, // SynchExtAbtOnTranslTableWalkL0
156 0x15, // SynchExtAbtOnTranslTableWalkL1
157 0x16, // SynchExtAbtOnTranslTableWalkL2
158 0x17, // SynchExtAbtOnTranslTableWalkL3
159 0x1c, // SynchPtyErrOnTranslTableWalkL0
160 0x1d, // SynchPtyErrOnTranslTableWalkL1
161 0x1e, // SynchPtyErrOnTranslTableWalkL2
162 0x1f, // SynchPtyErrOnTranslTableWalkL3
163 0x04, // TranslationL0
164 0x05, // TranslationL1
165 0x06, // TranslationL2
166 0x07, // TranslationL3
167 0x08, // AccessFlagL0
168 0x09, // AccessFlagL1
169 0x0a, // AccessFlagL2
170 0x0b, // AccessFlagL3
171 // @todo: Section & Page Domain Fault in AArch64?
172 0xff, // DomainL0 (INVALID)
173 0xff, // DomainL1 (INVALID)
174 0xff, // DomainL2 (INVALID)
175 0xff, // DomainL3 (INVALID)
176 0x0c, // PermissionL0
177 0x0d, // PermissionL1
178 0x0e, // PermissionL2
179 0x0f, // PermissionL3
180 0xff, // DebugEvent (INVALID)
181 0x10, // SynchronousExternalAbort
182 0x30, // TLBConflictAbort
183 0x18, // SynchPtyErrOnMemoryAccess
184 0xff, // AsynchronousExternalAbort (INVALID)
185 0xff, // AsynchPtyErrOnMemoryAccess (INVALID)
186 0x00, // AddressSizeL0
187 0x01, // AddressSizeL1
188 0x02, // AddressSizeL2
189 0x03, // AddressSizeL3
190 0x40, // PrefetchTLBMiss
191 0x80 // PrefetchUncacheable
194 static_assert(sizeof(ArmFault::aarch64FaultSources
) ==
195 ArmFault::NumFaultSources
,
196 "Invalid size of ArmFault::aarch64FaultSources[]");
198 // Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode,
199 // {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap,
200 // {A, F} disable, class, stat
201 template<> ArmFault::FaultVals ArmFaultVals
<Reset
>::vals
= {
202 // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED
203 // location in AArch64)
204 "Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC
,
205 0, 0, 0, 0, false, true, true, EC_UNKNOWN
, FaultStat()
207 template<> ArmFault::FaultVals ArmFaultVals
<UndefinedInstruction
>::vals
= {
208 "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED
,
209 4, 2, 0, 0, true, false, false, EC_UNKNOWN
, FaultStat()
211 template<> ArmFault::FaultVals ArmFaultVals
<SupervisorCall
>::vals
= {
212 "Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC
,
213 4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP
, FaultStat()
215 template<> ArmFault::FaultVals ArmFaultVals
<SecureMonitorCall
>::vals
= {
216 "Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON
,
217 4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP
, FaultStat()
219 template<> ArmFault::FaultVals ArmFaultVals
<HypervisorCall
>::vals
= {
220 "Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP
,
221 4, 4, 4, 4, true, false, false, EC_HVC
, FaultStat()
223 template<> ArmFault::FaultVals ArmFaultVals
<PrefetchAbort
>::vals
= {
224 "Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT
,
225 4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP
, FaultStat()
227 template<> ArmFault::FaultVals ArmFaultVals
<DataAbort
>::vals
= {
228 "Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT
,
229 8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP
, FaultStat()
231 template<> ArmFault::FaultVals ArmFaultVals
<VirtualDataAbort
>::vals
= {
232 "Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT
,
233 8, 8, 0, 0, true, true, false, EC_INVALID
, FaultStat()
235 template<> ArmFault::FaultVals ArmFaultVals
<HypervisorTrap
>::vals
= {
236 // @todo: double check these values
237 "Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP
,
238 0, 0, 0, 0, false, false, false, EC_UNKNOWN
, FaultStat()
240 template<> ArmFault::FaultVals ArmFaultVals
<Interrupt
>::vals
= {
241 "IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ
,
242 4, 4, 0, 0, false, true, false, EC_UNKNOWN
, FaultStat()
244 template<> ArmFault::FaultVals ArmFaultVals
<VirtualInterrupt
>::vals
= {
245 "Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ
,
246 4, 4, 0, 0, false, true, false, EC_INVALID
, FaultStat()
248 template<> ArmFault::FaultVals ArmFaultVals
<FastInterrupt
>::vals
= {
249 "FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ
,
250 4, 4, 0, 0, false, true, true, EC_UNKNOWN
, FaultStat()
252 template<> ArmFault::FaultVals ArmFaultVals
<VirtualFastInterrupt
>::vals
= {
253 "Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ
,
254 4, 4, 0, 0, false, true, true, EC_INVALID
, FaultStat()
256 template<> ArmFault::FaultVals ArmFaultVals
<SupervisorTrap
>::vals
= {
257 // Some dummy values (SupervisorTrap is AArch64-only)
258 "Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC
,
259 0, 0, 0, 0, false, false, false, EC_UNKNOWN
, FaultStat()
261 template<> ArmFault::FaultVals ArmFaultVals
<SecureMonitorTrap
>::vals
= {
262 // Some dummy values (SecureMonitorTrap is AArch64-only)
263 "Secure Monitor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_MON
,
264 0, 0, 0, 0, false, false, false, EC_UNKNOWN
, FaultStat()
266 template<> ArmFault::FaultVals ArmFaultVals
<PCAlignmentFault
>::vals
= {
267 // Some dummy values (PCAlignmentFault is AArch64-only)
268 "PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC
,
269 0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT
, FaultStat()
271 template<> ArmFault::FaultVals ArmFaultVals
<SPAlignmentFault
>::vals
= {
272 // Some dummy values (SPAlignmentFault is AArch64-only)
273 "SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC
,
274 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT
, FaultStat()
276 template<> ArmFault::FaultVals ArmFaultVals
<SystemError
>::vals
= {
277 // Some dummy values (SError is AArch64-only)
278 "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC
,
279 0, 0, 0, 0, false, true, true, EC_SERROR
, FaultStat()
281 template<> ArmFault::FaultVals ArmFaultVals
<SoftwareBreakpoint
>::vals
= {
282 // Some dummy values (SoftwareBreakpoint is AArch64-only)
283 "Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC
,
284 0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT
, FaultStat()
286 template<> ArmFault::FaultVals ArmFaultVals
<ArmSev
>::vals
= {
288 "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC
,
289 0, 0, 0, 0, false, true, true, EC_UNKNOWN
, FaultStat()
291 template<> ArmFault::FaultVals ArmFaultVals
<IllegalInstSetStateFault
>::vals
= {
292 // Some dummy values (SPAlignmentFault is AArch64-only)
293 "Illegal Inst Set State Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC
,
294 0, 0, 0, 0, true, false, false, EC_ILLEGAL_INST
, FaultStat()
298 ArmFault::getVector(ThreadContext
*tc
)
302 // ARM ARM issue C B1.8.1
303 bool haveSecurity
= ArmSystem::haveSecurity(tc
);
305 // panic if SCTLR.VE because I have no idea what to do with vectored
307 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR
);
309 // Check for invalid modes
310 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
311 assert(haveSecurity
|| cpsr
.mode
!= MODE_MON
);
312 assert(ArmSystem::haveVirtualization(tc
) || cpsr
.mode
!= MODE_HYP
);
317 base
= tc
->readMiscReg(MISCREG_MVBAR
);
320 base
= tc
->readMiscReg(MISCREG_HVBAR
);
326 base
= haveSecurity
? tc
->readMiscReg(MISCREG_VBAR
) : 0;
330 return base
+ offset(tc
);
334 ArmFault::getVector64(ThreadContext
*tc
)
339 assert(ArmSystem::haveSecurity(tc
));
340 vbar
= tc
->readMiscReg(MISCREG_VBAR_EL3
);
343 assert(ArmSystem::haveVirtualization(tc
));
344 vbar
= tc
->readMiscReg(MISCREG_VBAR_EL2
);
347 vbar
= tc
->readMiscReg(MISCREG_VBAR_EL1
);
350 panic("Invalid target exception level");
353 return vbar
+ offset64();
357 ArmFault::getSyndromeReg64() const
361 return MISCREG_ESR_EL1
;
363 return MISCREG_ESR_EL2
;
365 return MISCREG_ESR_EL3
;
367 panic("Invalid exception level");
373 ArmFault::getFaultAddrReg64() const
377 return MISCREG_FAR_EL1
;
379 return MISCREG_FAR_EL2
;
381 return MISCREG_FAR_EL3
;
383 panic("Invalid exception level");
389 ArmFault::setSyndrome(ThreadContext
*tc
, MiscRegIndex syndrome_reg
)
392 uint32_t exc_class
= (uint32_t) ec(tc
);
393 uint32_t issVal
= iss();
394 assert(!from64
|| ArmSystem::highestELIs64(tc
));
396 value
= exc_class
<< 26;
398 // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24,
399 // 0x25) for which the ISS information is not valid (ARMv7).
400 // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not
401 // valid it is treated as RES1.
404 } else if ((bits(exc_class
, 5, 3) != 4) ||
405 (bits(exc_class
, 2) && bits(issVal
, 24))) {
406 if (!machInst
.thumb
|| machInst
.bigThumb
)
409 // Condition code valid for EC[5:4] nonzero
410 if (!from64
&& ((bits(exc_class
, 5, 4) == 0) &&
411 (bits(exc_class
, 3, 0) != 0))) {
412 if (!machInst
.thumb
) {
414 ConditionCode condCode
= (ConditionCode
) (uint32_t) machInst
.condCode
;
415 // If its on unconditional instruction report with a cond code of
416 // 0xE, ie the unconditional code
417 cond
= (condCode
== COND_UC
) ? COND_AL
: condCode
;
421 value
|= bits(issVal
, 19, 0);
425 tc
->setMiscReg(syndrome_reg
, value
);
429 ArmFault::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
431 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
433 if (ArmSystem::highestELIs64(tc
)) { // ARMv8
434 // Determine source exception level and mode
435 fromMode
= (OperatingMode
) (uint8_t) cpsr
.mode
;
436 fromEL
= opModeToEL(fromMode
);
437 if (opModeIs64(fromMode
))
440 // Determine target exception level
441 if (ArmSystem::haveSecurity(tc
) && routeToMonitor(tc
))
443 else if (ArmSystem::haveVirtualization(tc
) && routeToHyp(tc
))
446 toEL
= opModeToEL(nextMode());
450 if (toEL
== ArmSystem::highestEL(tc
) || ELIs64(tc
, toEL
)) {
451 // Invoke exception handler in AArch64 state
458 // ARMv7 (ARM ARM issue C B1.9)
460 bool have_security
= ArmSystem::haveSecurity(tc
);
461 bool have_virtualization
= ArmSystem::haveVirtualization(tc
);
463 FaultBase::invoke(tc
);
468 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR
);
469 SCR scr
= tc
->readMiscReg(MISCREG_SCR
);
470 CPSR saved_cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
471 saved_cpsr
.nz
= tc
->readCCReg(CCREG_NZ
);
472 saved_cpsr
.c
= tc
->readCCReg(CCREG_C
);
473 saved_cpsr
.v
= tc
->readCCReg(CCREG_V
);
474 saved_cpsr
.ge
= tc
->readCCReg(CCREG_GE
);
476 Addr curPc M5_VAR_USED
= tc
->pcState().pc();
477 ITSTATE it
= tc
->pcState().itstate();
478 saved_cpsr
.it2
= it
.top6
;
479 saved_cpsr
.it1
= it
.bottom2
;
481 // if we have a valid instruction then use it to annotate this fault with
482 // extra information. This is used to generate the correct fault syndrome
485 ArmStaticInst
*armInst
= reinterpret_cast<ArmStaticInst
*>(inst
.get());
486 armInst
->annotateFault(this);
489 if (have_security
&& routeToMonitor(tc
))
490 cpsr
.mode
= MODE_MON
;
491 else if (have_virtualization
&& routeToHyp(tc
))
492 cpsr
.mode
= MODE_HYP
;
494 cpsr
.mode
= nextMode();
496 // Ensure Secure state if initially in Monitor mode
497 if (have_security
&& saved_cpsr
.mode
== MODE_MON
) {
498 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
501 tc
->setMiscRegNoEffect(MISCREG_SCR
, scr
);
505 // some bits are set differently if we have been routed to hyp mode
506 if (cpsr
.mode
== MODE_HYP
) {
507 SCTLR hsctlr
= tc
->readMiscReg(MISCREG_HSCTLR
);
510 if (!scr
.ea
) {cpsr
.a
= 1;}
511 if (!scr
.fiq
) {cpsr
.f
= 1;}
512 if (!scr
.irq
) {cpsr
.i
= 1;}
513 } else if (cpsr
.mode
== MODE_MON
) {
514 // Special case handling when entering monitor mode
524 // The *Disable functions are virtual and different per fault
525 cpsr
.a
= cpsr
.a
| abortDisable(tc
);
526 cpsr
.f
= cpsr
.f
| fiqDisable(tc
);
529 cpsr
.it1
= cpsr
.it2
= 0;
531 tc
->setMiscReg(MISCREG_CPSR
, cpsr
);
533 // Make sure mailbox sets to one always
534 tc
->setMiscReg(MISCREG_SEV_MAILBOX
, 1);
536 // Clear the exclusive monitor
537 tc
->setMiscReg(MISCREG_LOCKFLAG
, 0);
539 if (cpsr
.mode
== MODE_HYP
) {
540 tc
->setMiscReg(MISCREG_ELR_HYP
, curPc
+
541 (saved_cpsr
.t
? thumbPcOffset(true) : armPcOffset(true)));
543 tc
->setIntReg(INTREG_LR
, curPc
+
544 (saved_cpsr
.t
? thumbPcOffset(false) : armPcOffset(false)));
549 tc
->setMiscReg(MISCREG_SPSR_FIQ
, saved_cpsr
);
552 tc
->setMiscReg(MISCREG_SPSR_IRQ
, saved_cpsr
);
555 tc
->setMiscReg(MISCREG_SPSR_SVC
, saved_cpsr
);
558 assert(have_security
);
559 tc
->setMiscReg(MISCREG_SPSR_MON
, saved_cpsr
);
562 tc
->setMiscReg(MISCREG_SPSR_ABT
, saved_cpsr
);
565 tc
->setMiscReg(MISCREG_SPSR_UND
, saved_cpsr
);
566 if (ec(tc
) != EC_UNKNOWN
)
567 setSyndrome(tc
, MISCREG_HSR
);
570 assert(have_virtualization
);
571 tc
->setMiscReg(MISCREG_SPSR_HYP
, saved_cpsr
);
572 setSyndrome(tc
, MISCREG_HSR
);
575 panic("unknown Mode\n");
578 Addr newPc
= getVector(tc
);
579 DPRINTF(Faults
, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
580 name(), cpsr
, curPc
, tc
->readIntReg(INTREG_LR
), newPc
);
583 pc
.nextThumb(pc
.thumb());
585 pc
.nextJazelle(pc
.jazelle());
586 pc
.aarch64(!cpsr
.width
);
587 pc
.nextAArch64(!cpsr
.width
);
592 ArmFault::invoke64(ThreadContext
*tc
, const StaticInstPtr
&inst
)
594 // Determine actual misc. register indices for ELR_ELx and SPSR_ELx
595 MiscRegIndex elr_idx
, spsr_idx
;
598 elr_idx
= MISCREG_ELR_EL1
;
599 spsr_idx
= MISCREG_SPSR_EL1
;
602 assert(ArmSystem::haveVirtualization(tc
));
603 elr_idx
= MISCREG_ELR_EL2
;
604 spsr_idx
= MISCREG_SPSR_EL2
;
607 assert(ArmSystem::haveSecurity(tc
));
608 elr_idx
= MISCREG_ELR_EL3
;
609 spsr_idx
= MISCREG_SPSR_EL3
;
612 panic("Invalid target exception level");
616 // Save process state into SPSR_ELx
617 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
619 spsr
.nz
= tc
->readCCReg(CCREG_NZ
);
620 spsr
.c
= tc
->readCCReg(CCREG_C
);
621 spsr
.v
= tc
->readCCReg(CCREG_V
);
623 // Force some bitfields to 0
632 spsr
.ge
= tc
->readCCReg(CCREG_GE
);
633 ITSTATE it
= tc
->pcState().itstate();
635 spsr
.it1
= it
.bottom2
;
636 // Force some bitfields to 0
640 tc
->setMiscReg(spsr_idx
, spsr
);
642 // Save preferred return address into ELR_ELx
643 Addr curr_pc
= tc
->pcState().pc();
644 Addr ret_addr
= curr_pc
;
646 ret_addr
+= armPcElrOffset();
648 ret_addr
+= spsr
.t
? thumbPcElrOffset() : armPcElrOffset();
649 tc
->setMiscReg(elr_idx
, ret_addr
);
651 // Update process state
652 OperatingMode64 mode
= 0;
660 tc
->setMiscReg(MISCREG_CPSR
, cpsr
);
662 // Set PC to start of exception handler
663 Addr new_pc
= purifyTaggedAddr(getVector64(tc
), tc
, toEL
);
664 DPRINTF(Faults
, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x "
665 "elr:%#x newVec: %#x\n", name(), cpsr
, curr_pc
, ret_addr
, new_pc
);
667 pc
.aarch64(!cpsr
.width
);
668 pc
.nextAArch64(!cpsr
.width
);
671 // If we have a valid instruction then use it to annotate this fault with
672 // extra information. This is used to generate the correct fault syndrome
675 reinterpret_cast<ArmStaticInst
*>(inst
.get())->annotateFault(this);
676 // Save exception syndrome
677 if ((nextMode() != MODE_IRQ
) && (nextMode() != MODE_FIQ
))
678 setSyndrome(tc
, getSyndromeReg64());
682 Reset::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
685 tc
->getCpuPtr()->clearInterrupts(tc
->threadId());
688 if (!ArmSystem::highestELIs64(tc
)) {
689 ArmFault::invoke(tc
, inst
);
690 tc
->setMiscReg(MISCREG_VMPIDR
,
691 getMPIDR(dynamic_cast<ArmSystem
*>(tc
->getSystemPtr()), tc
));
693 // Unless we have SMC code to get us there, boot in HYP!
694 if (ArmSystem::haveVirtualization(tc
) &&
695 !ArmSystem::haveSecurity(tc
)) {
696 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
697 cpsr
.mode
= MODE_HYP
;
698 tc
->setMiscReg(MISCREG_CPSR
, cpsr
);
701 // Advance the PC to the IMPLEMENTATION DEFINED reset value
702 PCState pc
= ArmSystem::resetAddr64(tc
);
704 pc
.nextAArch64(true);
710 UndefinedInstruction::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
713 ArmFault::invoke(tc
, inst
);
717 // If the mnemonic isn't defined this has to be an unknown instruction.
718 assert(unknown
|| mnemonic
!= NULL
);
720 panic("Attempted to execute disabled instruction "
721 "'%s' (inst 0x%08x)", mnemonic
, machInst
);
722 } else if (unknown
) {
723 panic("Attempted to execute unknown instruction (inst 0x%08x)",
726 panic("Attempted to execute unimplemented instruction "
727 "'%s' (inst 0x%08x)", mnemonic
, machInst
);
732 UndefinedInstruction::routeToHyp(ThreadContext
*tc
) const
736 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
737 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
738 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
740 // if in Hyp mode then stay in Hyp mode
741 toHyp
= scr
.ns
&& (cpsr
.mode
== MODE_HYP
);
742 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
743 toHyp
|= !inSecureState(scr
, cpsr
) && hcr
.tge
&& (cpsr
.mode
== MODE_USER
);
748 UndefinedInstruction::iss() const
750 if (overrideEc
== EC_INVALID
)
753 uint32_t new_iss
= 0;
754 uint32_t op0
, op1
, op2
, CRn
, CRm
, Rt
, dir
;
756 dir
= bits(machInst
, 21, 21);
757 op0
= bits(machInst
, 20, 19);
758 op1
= bits(machInst
, 18, 16);
759 CRn
= bits(machInst
, 15, 12);
760 CRm
= bits(machInst
, 11, 8);
761 op2
= bits(machInst
, 7, 5);
762 Rt
= bits(machInst
, 4, 0);
764 new_iss
= op0
<< 20 | op2
<< 17 | op1
<< 14 | CRn
<< 10 |
765 Rt
<< 5 | CRm
<< 1 | dir
;
771 SupervisorCall::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
774 ArmFault::invoke(tc
, inst
);
778 // As of now, there isn't a 32 bit thumb version of this instruction.
779 assert(!machInst
.bigThumb
);
781 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
782 OperatingMode mode
= (OperatingMode
)(uint8_t)cpsr
.mode
;
783 if (opModeIs64(mode
))
784 callNum
= tc
->readIntReg(INTREG_X8
);
786 callNum
= tc
->readIntReg(INTREG_R7
);
788 tc
->syscall(callNum
, &fault
);
790 // Advance the PC since that won't happen automatically.
791 PCState pc
= tc
->pcState();
798 SupervisorCall::routeToHyp(ThreadContext
*tc
) const
802 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
803 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
804 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
806 // if in Hyp mode then stay in Hyp mode
807 toHyp
= scr
.ns
&& (cpsr
.mode
== MODE_HYP
);
808 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
809 toHyp
|= !inSecureState(scr
, cpsr
) && hcr
.tge
&& (cpsr
.mode
== MODE_USER
);
814 SupervisorCall::ec(ThreadContext
*tc
) const
816 return (overrideEc
!= EC_INVALID
) ? overrideEc
:
817 (from64
? EC_SVC_64
: vals
.ec
);
821 SupervisorCall::iss() const
823 // Even if we have a 24 bit imm from an arm32 instruction then we only use
824 // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC).
825 return issRaw
& 0xFFFF;
829 SecureMonitorCall::iss() const
832 return bits(machInst
, 20, 5);
837 UndefinedInstruction::ec(ThreadContext
*tc
) const
839 return (overrideEc
!= EC_INVALID
) ? overrideEc
: vals
.ec
;
843 HypervisorCall::HypervisorCall(ExtMachInst _machInst
, uint32_t _imm
) :
844 ArmFaultVals
<HypervisorCall
>(_machInst
, _imm
)
848 HypervisorCall::ec(ThreadContext
*tc
) const
850 return from64
? EC_HVC_64
: vals
.ec
;
854 HypervisorTrap::ec(ThreadContext
*tc
) const
856 return (overrideEc
!= EC_INVALID
) ? overrideEc
: vals
.ec
;
861 ArmFaultVals
<T
>::offset(ThreadContext
*tc
)
863 bool isHypTrap
= false;
865 // Normally we just use the exception vector from the table at the top if
866 // this file, however if this exception has caused a transition to hype
867 // mode, and its an exception type that would only do this if it has been
868 // trapped then we use the hyp trap vector instead of the normal vector
869 if (vals
.hypTrappable
) {
870 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
871 if (cpsr
.mode
== MODE_HYP
) {
872 CPSR spsr
= tc
->readMiscReg(MISCREG_SPSR_HYP
);
873 isHypTrap
= spsr
.mode
!= MODE_HYP
;
876 return isHypTrap
? 0x14 : vals
.offset
;
880 // SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx)
883 // esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32;
884 // esr.il = !machInst.thumb;
885 // if (machInst.aarch64)
886 // esr.imm16 = bits(machInst.instBits, 20, 5);
887 // else if (machInst.thumb)
888 // esr.imm16 = bits(machInst.instBits, 7, 0);
890 // esr.imm16 = bits(machInst.instBits, 15, 0);
891 // tc->setMiscReg(esr_idx, esr);
895 SecureMonitorCall::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
898 ArmFault::invoke(tc
, inst
);
904 SecureMonitorCall::ec(ThreadContext
*tc
) const
906 return (from64
? EC_SMC_64
: vals
.ec
);
910 SupervisorTrap::ec(ThreadContext
*tc
) const
912 return (overrideEc
!= EC_INVALID
) ? overrideEc
: vals
.ec
;
916 SecureMonitorTrap::ec(ThreadContext
*tc
) const
918 return (overrideEc
!= EC_INVALID
) ? overrideEc
:
919 (from64
? EC_SMC_64
: vals
.ec
);
924 AbortFault
<T
>::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
926 if (tranMethod
== ArmFault::UnknownTran
) {
927 tranMethod
= longDescFormatInUse(tc
) ? ArmFault::LpaeTran
928 : ArmFault::VmsaTran
;
930 if ((tranMethod
== ArmFault::VmsaTran
) && this->routeToMonitor(tc
)) {
931 // See ARM ARM B3-1416
932 bool override_LPAE
= false;
933 TTBCR ttbcr_s
= tc
->readMiscReg(MISCREG_TTBCR_S
);
934 TTBCR M5_VAR_USED ttbcr_ns
= tc
->readMiscReg(MISCREG_TTBCR_NS
);
936 override_LPAE
= true;
938 // Unimplemented code option, not seen in testing. May need
939 // extension according to the manual exceprt above.
940 DPRINTF(Faults
, "Warning: Incomplete translation method "
941 "override detected.\n");
944 tranMethod
= ArmFault::LpaeTran
;
948 if (source
== ArmFault::AsynchronousExternalAbort
) {
949 tc
->getCpuPtr()->clearInterrupt(tc
->threadId(), INT_ABT
, 0);
951 // Get effective fault source encoding
952 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
953 FSR fsr
= getFsr(tc
);
955 // source must be determined BEFORE invoking generic routines which will
956 // try to set hsr etc. and are based upon source!
957 ArmFaultVals
<T
>::invoke(tc
, inst
);
959 if (!this->to64
) { // AArch32
960 if (cpsr
.mode
== MODE_HYP
) {
961 tc
->setMiscReg(T::HFarIndex
, faultAddr
);
963 tc
->setMiscReg(MISCREG_HPFAR
, (faultAddr
>> 8) & ~0xf);
964 tc
->setMiscReg(T::HFarIndex
, OVAddr
);
966 tc
->setMiscReg(T::FsrIndex
, fsr
);
967 tc
->setMiscReg(T::FarIndex
, faultAddr
);
969 DPRINTF(Faults
, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\
970 "tranMethod=%#x\n", source
, fsr
, faultAddr
, tranMethod
);
972 // Set the FAR register. Nothing else to do if we are in AArch64 state
973 // because the syndrome register has already been set inside invoke64()
975 // stage 2 fault, set HPFAR_EL2 to the faulting IPA
976 // and FAR_EL2 to the Original VA
977 tc
->setMiscReg(AbortFault
<T
>::getFaultAddrReg64(), OVAddr
);
978 tc
->setMiscReg(MISCREG_HPFAR_EL2
, bits(faultAddr
, 47, 12) << 4);
980 DPRINTF(Faults
, "Abort Fault (Stage 2) VA: 0x%x IPA: 0x%x\n",
983 tc
->setMiscReg(AbortFault
<T
>::getFaultAddrReg64(), faultAddr
);
990 AbortFault
<T
>::getFsr(ThreadContext
*tc
)
994 if (((CPSR
) tc
->readMiscRegNoEffect(MISCREG_CPSR
)).width
) {
996 assert(tranMethod
!= ArmFault::UnknownTran
);
997 if (tranMethod
== ArmFault::LpaeTran
) {
998 srcEncoded
= ArmFault::longDescFaultSources
[source
];
999 fsr
.status
= srcEncoded
;
1002 srcEncoded
= ArmFault::shortDescFaultSources
[source
];
1003 fsr
.fsLow
= bits(srcEncoded
, 3, 0);
1004 fsr
.fsHigh
= bits(srcEncoded
, 4);
1005 fsr
.domain
= static_cast<uint8_t>(domain
);
1007 fsr
.wnr
= (write
? 1 : 0);
1011 srcEncoded
= ArmFault::aarch64FaultSources
[source
];
1013 if (srcEncoded
== ArmFault::FaultSourceInvalid
) {
1014 panic("Invalid fault source\n");
1021 AbortFault
<T
>::abortDisable(ThreadContext
*tc
)
1023 if (ArmSystem::haveSecurity(tc
)) {
1024 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1025 return (!scr
.ns
|| scr
.aw
);
1032 AbortFault
<T
>::annotate(ArmFault::AnnotationIDs id
, uint64_t val
)
1036 case ArmFault::S1PTW
:
1043 // Just ignore unknown ID's
1051 AbortFault
<T
>::iss() const
1055 val
= srcEncoded
& 0x3F;
1063 AbortFault
<T
>::isMMUFault() const
1065 // NOTE: Not relying on LL information being aligned to lowest bits here
1067 (source
== ArmFault::AlignmentFault
) ||
1068 ((source
>= ArmFault::TranslationLL
) &&
1069 (source
< ArmFault::TranslationLL
+ 4)) ||
1070 ((source
>= ArmFault::AccessFlagLL
) &&
1071 (source
< ArmFault::AccessFlagLL
+ 4)) ||
1072 ((source
>= ArmFault::DomainLL
) &&
1073 (source
< ArmFault::DomainLL
+ 4)) ||
1074 ((source
>= ArmFault::PermissionLL
) &&
1075 (source
< ArmFault::PermissionLL
+ 4));
1079 PrefetchAbort::ec(ThreadContext
*tc
) const
1084 return EC_PREFETCH_ABORT_CURR_EL
;
1086 return EC_PREFETCH_ABORT_LOWER_EL
;
1089 // Abort faults have different EC codes depending on whether
1090 // the fault originated within HYP mode, or not. So override
1091 // the method and add the extra adjustment of the EC value.
1093 ExceptionClass ec
= ArmFaultVals
<PrefetchAbort
>::vals
.ec
;
1095 CPSR spsr
= tc
->readMiscReg(MISCREG_SPSR_HYP
);
1096 if (spsr
.mode
== MODE_HYP
) {
1097 ec
= ((ExceptionClass
) (((uint32_t) ec
) + 1));
1104 PrefetchAbort::routeToMonitor(ThreadContext
*tc
) const
1108 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1110 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1112 return scr
.ea
&& !isMMUFault();
1116 PrefetchAbort::routeToHyp(ThreadContext
*tc
) const
1120 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1121 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
1122 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
1123 HDCR hdcr
= tc
->readMiscRegNoEffect(MISCREG_HDCR
);
1125 // if in Hyp mode then stay in Hyp mode
1126 toHyp
= scr
.ns
&& (cpsr
.mode
== MODE_HYP
);
1127 // otherwise, check whether to take to Hyp mode through Hyp Trap vector
1129 ( (source
== DebugEvent
) && hdcr
.tde
&& (cpsr
.mode
!= MODE_HYP
)) ||
1130 ( (source
== SynchronousExternalAbort
) && hcr
.tge
&& (cpsr
.mode
== MODE_USER
))
1131 ) && !inSecureState(tc
);
1136 DataAbort::ec(ThreadContext
*tc
) const
1140 if (source
== ArmFault::AsynchronousExternalAbort
) {
1141 panic("Asynchronous External Abort should be handled with "
1142 "SystemErrors (SErrors)!");
1145 return EC_DATA_ABORT_CURR_EL
;
1147 return EC_DATA_ABORT_LOWER_EL
;
1150 // Abort faults have different EC codes depending on whether
1151 // the fault originated within HYP mode, or not. So override
1152 // the method and add the extra adjustment of the EC value.
1154 ExceptionClass ec
= ArmFaultVals
<DataAbort
>::vals
.ec
;
1156 CPSR spsr
= tc
->readMiscReg(MISCREG_SPSR_HYP
);
1157 if (spsr
.mode
== MODE_HYP
) {
1158 ec
= ((ExceptionClass
) (((uint32_t) ec
) + 1));
1165 DataAbort::routeToMonitor(ThreadContext
*tc
) const
1169 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1171 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1173 return scr
.ea
&& !isMMUFault();
1177 DataAbort::routeToHyp(ThreadContext
*tc
) const
1181 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1182 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
1183 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
1184 HDCR hdcr
= tc
->readMiscRegNoEffect(MISCREG_HDCR
);
1186 // if in Hyp mode then stay in Hyp mode
1187 toHyp
= scr
.ns
&& (cpsr
.mode
== MODE_HYP
);
1188 // otherwise, check whether to take to Hyp mode through Hyp Trap vector
1190 ( (cpsr
.mode
!= MODE_HYP
) && ( ((source
== AsynchronousExternalAbort
) && hcr
.amo
) ||
1191 ((source
== DebugEvent
) && hdcr
.tde
) )
1193 ( (cpsr
.mode
== MODE_USER
) && hcr
.tge
&&
1194 ((source
== AlignmentFault
) ||
1195 (source
== SynchronousExternalAbort
))
1197 ) && !inSecureState(tc
);
1202 DataAbort::iss() const
1206 // Add on the data abort specific fields to the generic abort ISS value
1207 val
= AbortFault
<DataAbort
>::iss();
1208 // ISS is valid if not caused by a stage 1 page table walk, and when taken
1209 // to AArch64 only when directed to EL2
1210 if (!s1ptw
&& (!to64
|| toEL
== EL2
)) {
1216 // AArch64 only. These assignments are safe on AArch32 as well
1217 // because these vars are initialized to false
1226 DataAbort::annotate(AnnotationIDs id
, uint64_t val
)
1228 AbortFault
<DataAbort
>::annotate(id
, val
);
1251 // Just ignore unknown ID's
1258 VirtualDataAbort::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
1260 AbortFault
<VirtualDataAbort
>::invoke(tc
, inst
);
1261 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
1263 tc
->setMiscRegNoEffect(MISCREG_HCR
, hcr
);
1267 Interrupt::routeToMonitor(ThreadContext
*tc
) const
1269 assert(ArmSystem::haveSecurity(tc
));
1272 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1274 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1279 Interrupt::routeToHyp(ThreadContext
*tc
) const
1283 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1284 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
1285 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
1286 // Determine whether IRQs are routed to Hyp mode.
1287 toHyp
= (!scr
.irq
&& hcr
.imo
&& !inSecureState(tc
)) ||
1288 (cpsr
.mode
== MODE_HYP
);
1293 Interrupt::abortDisable(ThreadContext
*tc
)
1295 if (ArmSystem::haveSecurity(tc
)) {
1296 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1297 return (!scr
.ns
|| scr
.aw
);
1302 VirtualInterrupt::VirtualInterrupt()
1306 FastInterrupt::routeToMonitor(ThreadContext
*tc
) const
1308 assert(ArmSystem::haveSecurity(tc
));
1311 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1313 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1318 FastInterrupt::routeToHyp(ThreadContext
*tc
) const
1322 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1323 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
1324 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
1325 // Determine whether IRQs are routed to Hyp mode.
1326 toHyp
= (!scr
.fiq
&& hcr
.fmo
&& !inSecureState(tc
)) ||
1327 (cpsr
.mode
== MODE_HYP
);
1332 FastInterrupt::abortDisable(ThreadContext
*tc
)
1334 if (ArmSystem::haveSecurity(tc
)) {
1335 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1336 return (!scr
.ns
|| scr
.aw
);
1342 FastInterrupt::fiqDisable(ThreadContext
*tc
)
1344 if (ArmSystem::haveVirtualization(tc
)) {
1346 } else if (ArmSystem::haveSecurity(tc
)) {
1347 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1348 return (!scr
.ns
|| scr
.fw
);
1353 VirtualFastInterrupt::VirtualFastInterrupt()
1357 PCAlignmentFault::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
1359 ArmFaultVals
<PCAlignmentFault
>::invoke(tc
, inst
);
1362 tc
->setMiscReg(getFaultAddrReg64(), faultPC
);
1365 SPAlignmentFault::SPAlignmentFault()
1368 SystemError::SystemError()
1372 SystemError::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
1374 tc
->getCpuPtr()->clearInterrupt(tc
->threadId(), INT_ABT
, 0);
1375 ArmFault::invoke(tc
, inst
);
1379 SystemError::routeToMonitor(ThreadContext
*tc
) const
1381 assert(ArmSystem::haveSecurity(tc
));
1383 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1388 SystemError::routeToHyp(ThreadContext
*tc
) const
1393 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1394 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
1396 toHyp
= (!scr
.ea
&& hcr
.amo
&& !inSecureState(tc
)) ||
1397 (!scr
.ea
&& !scr
.rw
&& !hcr
.amo
&& !inSecureState(tc
));
1402 SoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst _mach_inst
, uint32_t _iss
)
1403 : ArmFaultVals
<SoftwareBreakpoint
>(_mach_inst
, _iss
)
1407 SoftwareBreakpoint::routeToHyp(ThreadContext
*tc
) const
1411 const bool have_el2
= ArmSystem::haveVirtualization(tc
);
1413 const HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR_EL2
);
1414 const HDCR mdcr
= tc
->readMiscRegNoEffect(MISCREG_MDCR_EL2
);
1416 return have_el2
&& !inSecureState(tc
) && fromEL
<= EL1
&&
1417 (hcr
.tge
|| mdcr
.tde
);
1421 ArmSev::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
) {
1422 DPRINTF(Faults
, "Invoking ArmSev Fault\n");
1426 // Set sev_mailbox to 1, clear the pending interrupt from remote
1427 // SEV execution and let pipeline continue as pcState is still
1429 tc
->setMiscReg(MISCREG_SEV_MAILBOX
, 1);
1430 tc
->getCpuPtr()->clearInterrupt(tc
->threadId(), INT_SEV
, 0);
1433 // Instantiate all the templates to make the linker happy
1434 template class ArmFaultVals
<Reset
>;
1435 template class ArmFaultVals
<UndefinedInstruction
>;
1436 template class ArmFaultVals
<SupervisorCall
>;
1437 template class ArmFaultVals
<SecureMonitorCall
>;
1438 template class ArmFaultVals
<HypervisorCall
>;
1439 template class ArmFaultVals
<PrefetchAbort
>;
1440 template class ArmFaultVals
<DataAbort
>;
1441 template class ArmFaultVals
<VirtualDataAbort
>;
1442 template class ArmFaultVals
<HypervisorTrap
>;
1443 template class ArmFaultVals
<Interrupt
>;
1444 template class ArmFaultVals
<VirtualInterrupt
>;
1445 template class ArmFaultVals
<FastInterrupt
>;
1446 template class ArmFaultVals
<VirtualFastInterrupt
>;
1447 template class ArmFaultVals
<SupervisorTrap
>;
1448 template class ArmFaultVals
<SecureMonitorTrap
>;
1449 template class ArmFaultVals
<PCAlignmentFault
>;
1450 template class ArmFaultVals
<SPAlignmentFault
>;
1451 template class ArmFaultVals
<SystemError
>;
1452 template class ArmFaultVals
<SoftwareBreakpoint
>;
1453 template class ArmFaultVals
<ArmSev
>;
1454 template class AbortFault
<PrefetchAbort
>;
1455 template class AbortFault
<DataAbort
>;
1456 template class AbortFault
<VirtualDataAbort
>;
1459 IllegalInstSetStateFault::IllegalInstSetStateFault()
1463 } // namespace ArmISA