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15 * Copyright (c) 2007-2008 The Florida State University
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47 #include "arch/arm/faults.hh"
48 #include "arch/arm/system.hh"
49 #include "arch/arm/utility.hh"
50 #include "arch/arm/insts/static_inst.hh"
51 #include "base/compiler.hh"
52 #include "base/trace.hh"
53 #include "cpu/base.hh"
54 #include "cpu/thread_context.hh"
55 #include "debug/Faults.hh"
56 #include "sim/full_system.hh"
61 uint8_t ArmFault::shortDescFaultSources
[] = {
62 0x01, // AlignmentFault
63 0x04, // InstructionCacheMaintenance
64 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID)
65 0x0c, // SynchExtAbtOnTranslTableWalkL1
66 0x0e, // SynchExtAbtOnTranslTableWalkL2
67 0xff, // SynchExtAbtOnTranslTableWalkL3 (INVALID)
68 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID)
69 0x1c, // SynchPtyErrOnTranslTableWalkL1
70 0x1e, // SynchPtyErrOnTranslTableWalkL2
71 0xff, // SynchPtyErrOnTranslTableWalkL3 (INVALID)
72 0xff, // TranslationL0 (INVALID)
73 0x05, // TranslationL1
74 0x07, // TranslationL2
75 0xff, // TranslationL3 (INVALID)
76 0xff, // AccessFlagL0 (INVALID)
79 0xff, // AccessFlagL3 (INVALID)
80 0xff, // DomainL0 (INVALID)
83 0xff, // DomainL3 (INVALID)
84 0xff, // PermissionL0 (INVALID)
87 0xff, // PermissionL3 (INVALID)
89 0x08, // SynchronousExternalAbort
90 0x10, // TLBConflictAbort
91 0x19, // SynchPtyErrOnMemoryAccess
92 0x16, // AsynchronousExternalAbort
93 0x18, // AsynchPtyErrOnMemoryAccess
94 0xff, // AddressSizeL0 (INVALID)
95 0xff, // AddressSizeL1 (INVALID)
96 0xff, // AddressSizeL2 (INVALID)
97 0xff, // AddressSizeL3 (INVALID)
98 0x40, // PrefetchTLBMiss
99 0x80 // PrefetchUncacheable
102 static_assert(sizeof(ArmFault::shortDescFaultSources
) ==
103 ArmFault::NumFaultSources
,
104 "Invalid size of ArmFault::shortDescFaultSources[]");
106 uint8_t ArmFault::longDescFaultSources
[] = {
107 0x21, // AlignmentFault
108 0xff, // InstructionCacheMaintenance (INVALID)
109 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID)
110 0x15, // SynchExtAbtOnTranslTableWalkL1
111 0x16, // SynchExtAbtOnTranslTableWalkL2
112 0x17, // SynchExtAbtOnTranslTableWalkL3
113 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID)
114 0x1d, // SynchPtyErrOnTranslTableWalkL1
115 0x1e, // SynchPtyErrOnTranslTableWalkL2
116 0x1f, // SynchPtyErrOnTranslTableWalkL3
117 0xff, // TranslationL0 (INVALID)
118 0x05, // TranslationL1
119 0x06, // TranslationL2
120 0x07, // TranslationL3
121 0xff, // AccessFlagL0 (INVALID)
122 0x09, // AccessFlagL1
123 0x0a, // AccessFlagL2
124 0x0b, // AccessFlagL3
125 0xff, // DomainL0 (INVALID)
128 0xff, // DomainL3 (RESERVED)
129 0xff, // PermissionL0 (INVALID)
130 0x0d, // PermissionL1
131 0x0e, // PermissionL2
132 0x0f, // PermissionL3
134 0x10, // SynchronousExternalAbort
135 0x30, // TLBConflictAbort
136 0x18, // SynchPtyErrOnMemoryAccess
137 0x11, // AsynchronousExternalAbort
138 0x19, // AsynchPtyErrOnMemoryAccess
139 0xff, // AddressSizeL0 (INVALID)
140 0xff, // AddressSizeL1 (INVALID)
141 0xff, // AddressSizeL2 (INVALID)
142 0xff, // AddressSizeL3 (INVALID)
143 0x40, // PrefetchTLBMiss
144 0x80 // PrefetchUncacheable
147 static_assert(sizeof(ArmFault::longDescFaultSources
) ==
148 ArmFault::NumFaultSources
,
149 "Invalid size of ArmFault::longDescFaultSources[]");
151 uint8_t ArmFault::aarch64FaultSources
[] = {
152 0x21, // AlignmentFault
153 0xff, // InstructionCacheMaintenance (INVALID)
154 0x14, // SynchExtAbtOnTranslTableWalkL0
155 0x15, // SynchExtAbtOnTranslTableWalkL1
156 0x16, // SynchExtAbtOnTranslTableWalkL2
157 0x17, // SynchExtAbtOnTranslTableWalkL3
158 0x1c, // SynchPtyErrOnTranslTableWalkL0
159 0x1d, // SynchPtyErrOnTranslTableWalkL1
160 0x1e, // SynchPtyErrOnTranslTableWalkL2
161 0x1f, // SynchPtyErrOnTranslTableWalkL3
162 0x04, // TranslationL0
163 0x05, // TranslationL1
164 0x06, // TranslationL2
165 0x07, // TranslationL3
166 0x08, // AccessFlagL0
167 0x09, // AccessFlagL1
168 0x0a, // AccessFlagL2
169 0x0b, // AccessFlagL3
170 // @todo: Section & Page Domain Fault in AArch64?
171 0xff, // DomainL0 (INVALID)
172 0xff, // DomainL1 (INVALID)
173 0xff, // DomainL2 (INVALID)
174 0xff, // DomainL3 (INVALID)
175 0x0c, // PermissionL0
176 0x0d, // PermissionL1
177 0x0e, // PermissionL2
178 0x0f, // PermissionL3
179 0xff, // DebugEvent (INVALID)
180 0x10, // SynchronousExternalAbort
181 0x30, // TLBConflictAbort
182 0x18, // SynchPtyErrOnMemoryAccess
183 0xff, // AsynchronousExternalAbort (INVALID)
184 0xff, // AsynchPtyErrOnMemoryAccess (INVALID)
185 0x00, // AddressSizeL0
186 0x01, // AddressSizeL1
187 0x02, // AddressSizeL2
188 0x03, // AddressSizeL3
189 0x40, // PrefetchTLBMiss
190 0x80 // PrefetchUncacheable
193 static_assert(sizeof(ArmFault::aarch64FaultSources
) ==
194 ArmFault::NumFaultSources
,
195 "Invalid size of ArmFault::aarch64FaultSources[]");
197 // Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode,
198 // {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap,
199 // {A, F} disable, class, stat
200 template<> ArmFault::FaultVals ArmFaultVals
<Reset
>::vals
= {
201 // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED
202 // location in AArch64)
203 "Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC
,
204 0, 0, 0, 0, false, true, true, EC_UNKNOWN
, FaultStat()
206 template<> ArmFault::FaultVals ArmFaultVals
<UndefinedInstruction
>::vals
= {
207 "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED
,
208 4, 2, 0, 0, true, false, false, EC_UNKNOWN
, FaultStat()
210 template<> ArmFault::FaultVals ArmFaultVals
<SupervisorCall
>::vals
= {
211 "Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC
,
212 4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP
, FaultStat()
214 template<> ArmFault::FaultVals ArmFaultVals
<SecureMonitorCall
>::vals
= {
215 "Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON
,
216 4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP
, FaultStat()
218 template<> ArmFault::FaultVals ArmFaultVals
<HypervisorCall
>::vals
= {
219 "Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP
,
220 4, 4, 4, 4, true, false, false, EC_HVC
, FaultStat()
222 template<> ArmFault::FaultVals ArmFaultVals
<PrefetchAbort
>::vals
= {
223 "Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT
,
224 4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP
, FaultStat()
226 template<> ArmFault::FaultVals ArmFaultVals
<DataAbort
>::vals
= {
227 "Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT
,
228 8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP
, FaultStat()
230 template<> ArmFault::FaultVals ArmFaultVals
<VirtualDataAbort
>::vals
= {
231 "Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT
,
232 8, 8, 0, 0, true, true, false, EC_INVALID
, FaultStat()
234 template<> ArmFault::FaultVals ArmFaultVals
<HypervisorTrap
>::vals
= {
235 // @todo: double check these values
236 "Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP
,
237 0, 0, 0, 0, false, false, false, EC_UNKNOWN
, FaultStat()
239 template<> ArmFault::FaultVals ArmFaultVals
<Interrupt
>::vals
= {
240 "IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ
,
241 4, 4, 0, 0, false, true, false, EC_UNKNOWN
, FaultStat()
243 template<> ArmFault::FaultVals ArmFaultVals
<VirtualInterrupt
>::vals
= {
244 "Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ
,
245 4, 4, 0, 0, false, true, false, EC_INVALID
, FaultStat()
247 template<> ArmFault::FaultVals ArmFaultVals
<FastInterrupt
>::vals
= {
248 "FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ
,
249 4, 4, 0, 0, false, true, true, EC_UNKNOWN
, FaultStat()
251 template<> ArmFault::FaultVals ArmFaultVals
<VirtualFastInterrupt
>::vals
= {
252 "Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ
,
253 4, 4, 0, 0, false, true, true, EC_INVALID
, FaultStat()
255 template<> ArmFault::FaultVals ArmFaultVals
<SupervisorTrap
>::vals
= {
256 // Some dummy values (SupervisorTrap is AArch64-only)
257 "Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC
,
258 0, 0, 0, 0, false, false, false, EC_UNKNOWN
, FaultStat()
260 template<> ArmFault::FaultVals ArmFaultVals
<SecureMonitorTrap
>::vals
= {
261 // Some dummy values (SecureMonitorTrap is AArch64-only)
262 "Secure Monitor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_MON
,
263 0, 0, 0, 0, false, false, false, EC_UNKNOWN
, FaultStat()
265 template<> ArmFault::FaultVals ArmFaultVals
<PCAlignmentFault
>::vals
= {
266 // Some dummy values (PCAlignmentFault is AArch64-only)
267 "PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC
,
268 0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT
, FaultStat()
270 template<> ArmFault::FaultVals ArmFaultVals
<SPAlignmentFault
>::vals
= {
271 // Some dummy values (SPAlignmentFault is AArch64-only)
272 "SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC
,
273 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT
, FaultStat()
275 template<> ArmFault::FaultVals ArmFaultVals
<SystemError
>::vals
= {
276 // Some dummy values (SError is AArch64-only)
277 "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC
,
278 0, 0, 0, 0, false, true, true, EC_SERROR
, FaultStat()
280 template<> ArmFault::FaultVals ArmFaultVals
<FlushPipe
>::vals
= {
282 "Pipe Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC
,
283 0, 0, 0, 0, false, true, true, EC_UNKNOWN
, FaultStat()
285 template<> ArmFault::FaultVals ArmFaultVals
<ArmSev
>::vals
= {
287 "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC
,
288 0, 0, 0, 0, false, true, true, EC_UNKNOWN
, FaultStat()
290 template<> ArmFault::FaultVals ArmFaultVals
<IllegalInstSetStateFault
>::vals
= {
291 // Some dummy values (SPAlignmentFault is AArch64-only)
292 "Illegal Inst Set State Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC
,
293 0, 0, 0, 0, true, false, false, EC_ILLEGAL_INST
, FaultStat()
297 ArmFault::getVector(ThreadContext
*tc
)
301 // ARM ARM issue C B1.8.1
302 bool haveSecurity
= ArmSystem::haveSecurity(tc
);
304 // panic if SCTLR.VE because I have no idea what to do with vectored
306 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR
);
308 // Check for invalid modes
309 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
310 assert(haveSecurity
|| cpsr
.mode
!= MODE_MON
);
311 assert(ArmSystem::haveVirtualization(tc
) || cpsr
.mode
!= MODE_HYP
);
316 base
= tc
->readMiscReg(MISCREG_MVBAR
);
319 base
= tc
->readMiscReg(MISCREG_HVBAR
);
325 base
= haveSecurity
? tc
->readMiscReg(MISCREG_VBAR
) : 0;
329 return base
+ offset(tc
);
333 ArmFault::getVector64(ThreadContext
*tc
)
338 assert(ArmSystem::haveSecurity(tc
));
339 vbar
= tc
->readMiscReg(MISCREG_VBAR_EL3
);
341 // @todo: uncomment this to enable Virtualization
343 // assert(ArmSystem::haveVirtualization(tc));
344 // vbar = tc->readMiscReg(MISCREG_VBAR_EL2);
347 vbar
= tc
->readMiscReg(MISCREG_VBAR_EL1
);
350 panic("Invalid target exception level");
353 return vbar
+ offset64();
357 ArmFault::getSyndromeReg64() const
361 return MISCREG_ESR_EL1
;
363 return MISCREG_ESR_EL2
;
365 return MISCREG_ESR_EL3
;
367 panic("Invalid exception level");
373 ArmFault::getFaultAddrReg64() const
377 return MISCREG_FAR_EL1
;
379 return MISCREG_FAR_EL2
;
381 return MISCREG_FAR_EL3
;
383 panic("Invalid exception level");
389 ArmFault::setSyndrome(ThreadContext
*tc
, MiscRegIndex syndrome_reg
)
392 uint32_t exc_class
= (uint32_t) ec(tc
);
393 uint32_t issVal
= iss();
394 assert(!from64
|| ArmSystem::highestELIs64(tc
));
396 value
= exc_class
<< 26;
398 // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24,
399 // 0x25) for which the ISS information is not valid (ARMv7).
400 // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not
401 // valid it is treated as RES1.
404 } else if ((bits(exc_class
, 5, 3) != 4) ||
405 (bits(exc_class
, 2) && bits(issVal
, 24))) {
406 if (!machInst
.thumb
|| machInst
.bigThumb
)
409 // Condition code valid for EC[5:4] nonzero
410 if (!from64
&& ((bits(exc_class
, 5, 4) == 0) &&
411 (bits(exc_class
, 3, 0) != 0))) {
412 if (!machInst
.thumb
) {
414 ConditionCode condCode
= (ConditionCode
) (uint32_t) machInst
.condCode
;
415 // If its on unconditional instruction report with a cond code of
416 // 0xE, ie the unconditional code
417 cond
= (condCode
== COND_UC
) ? COND_AL
: condCode
;
421 value
|= bits(issVal
, 19, 0);
425 tc
->setMiscReg(syndrome_reg
, value
);
429 ArmFault::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
431 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
433 if (ArmSystem::highestELIs64(tc
)) { // ARMv8
434 // Determine source exception level and mode
435 fromMode
= (OperatingMode
) (uint8_t) cpsr
.mode
;
436 fromEL
= opModeToEL(fromMode
);
437 if (opModeIs64(fromMode
))
440 // Determine target exception level
441 if (ArmSystem::haveSecurity(tc
) && routeToMonitor(tc
))
444 toEL
= opModeToEL(nextMode());
448 if (toEL
== ArmSystem::highestEL(tc
) || ELIs64(tc
, toEL
)) {
449 // Invoke exception handler in AArch64 state
456 // ARMv7 (ARM ARM issue C B1.9)
458 bool have_security
= ArmSystem::haveSecurity(tc
);
459 bool have_virtualization
= ArmSystem::haveVirtualization(tc
);
461 FaultBase::invoke(tc
);
466 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR
);
467 SCR scr
= tc
->readMiscReg(MISCREG_SCR
);
468 CPSR saved_cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
469 saved_cpsr
.nz
= tc
->readCCReg(CCREG_NZ
);
470 saved_cpsr
.c
= tc
->readCCReg(CCREG_C
);
471 saved_cpsr
.v
= tc
->readCCReg(CCREG_V
);
472 saved_cpsr
.ge
= tc
->readCCReg(CCREG_GE
);
474 Addr curPc M5_VAR_USED
= tc
->pcState().pc();
475 ITSTATE it
= tc
->pcState().itstate();
476 saved_cpsr
.it2
= it
.top6
;
477 saved_cpsr
.it1
= it
.bottom2
;
479 // if we have a valid instruction then use it to annotate this fault with
480 // extra information. This is used to generate the correct fault syndrome
483 ArmStaticInst
*armInst
= reinterpret_cast<ArmStaticInst
*>(inst
.get());
484 armInst
->annotateFault(this);
487 if (have_security
&& routeToMonitor(tc
))
488 cpsr
.mode
= MODE_MON
;
489 else if (have_virtualization
&& routeToHyp(tc
))
490 cpsr
.mode
= MODE_HYP
;
492 cpsr
.mode
= nextMode();
494 // Ensure Secure state if initially in Monitor mode
495 if (have_security
&& saved_cpsr
.mode
== MODE_MON
) {
496 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
499 tc
->setMiscRegNoEffect(MISCREG_SCR
, scr
);
503 // some bits are set differently if we have been routed to hyp mode
504 if (cpsr
.mode
== MODE_HYP
) {
505 SCTLR hsctlr
= tc
->readMiscReg(MISCREG_HSCTLR
);
508 if (!scr
.ea
) {cpsr
.a
= 1;}
509 if (!scr
.fiq
) {cpsr
.f
= 1;}
510 if (!scr
.irq
) {cpsr
.i
= 1;}
511 } else if (cpsr
.mode
== MODE_MON
) {
512 // Special case handling when entering monitor mode
522 // The *Disable functions are virtual and different per fault
523 cpsr
.a
= cpsr
.a
| abortDisable(tc
);
524 cpsr
.f
= cpsr
.f
| fiqDisable(tc
);
527 cpsr
.it1
= cpsr
.it2
= 0;
529 tc
->setMiscReg(MISCREG_CPSR
, cpsr
);
531 // Make sure mailbox sets to one always
532 tc
->setMiscReg(MISCREG_SEV_MAILBOX
, 1);
534 // Clear the exclusive monitor
535 tc
->setMiscReg(MISCREG_LOCKFLAG
, 0);
537 if (cpsr
.mode
== MODE_HYP
) {
538 tc
->setMiscReg(MISCREG_ELR_HYP
, curPc
+
539 (saved_cpsr
.t
? thumbPcOffset(true) : armPcOffset(true)));
541 tc
->setIntReg(INTREG_LR
, curPc
+
542 (saved_cpsr
.t
? thumbPcOffset(false) : armPcOffset(false)));
547 tc
->setMiscReg(MISCREG_SPSR_FIQ
, saved_cpsr
);
550 tc
->setMiscReg(MISCREG_SPSR_IRQ
, saved_cpsr
);
553 tc
->setMiscReg(MISCREG_SPSR_SVC
, saved_cpsr
);
556 assert(have_security
);
557 tc
->setMiscReg(MISCREG_SPSR_MON
, saved_cpsr
);
560 tc
->setMiscReg(MISCREG_SPSR_ABT
, saved_cpsr
);
563 tc
->setMiscReg(MISCREG_SPSR_UND
, saved_cpsr
);
564 if (ec(tc
) != EC_UNKNOWN
)
565 setSyndrome(tc
, MISCREG_HSR
);
568 assert(have_virtualization
);
569 tc
->setMiscReg(MISCREG_SPSR_HYP
, saved_cpsr
);
570 setSyndrome(tc
, MISCREG_HSR
);
573 panic("unknown Mode\n");
576 Addr newPc
= getVector(tc
);
577 DPRINTF(Faults
, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
578 name(), cpsr
, curPc
, tc
->readIntReg(INTREG_LR
), newPc
);
581 pc
.nextThumb(pc
.thumb());
583 pc
.nextJazelle(pc
.jazelle());
584 pc
.aarch64(!cpsr
.width
);
585 pc
.nextAArch64(!cpsr
.width
);
590 ArmFault::invoke64(ThreadContext
*tc
, const StaticInstPtr
&inst
)
592 // Determine actual misc. register indices for ELR_ELx and SPSR_ELx
593 MiscRegIndex elr_idx
, spsr_idx
;
596 elr_idx
= MISCREG_ELR_EL1
;
597 spsr_idx
= MISCREG_SPSR_EL1
;
599 // @todo: uncomment this to enable Virtualization
601 // assert(ArmSystem::haveVirtualization());
602 // elr_idx = MISCREG_ELR_EL2;
603 // spsr_idx = MISCREG_SPSR_EL2;
606 assert(ArmSystem::haveSecurity(tc
));
607 elr_idx
= MISCREG_ELR_EL3
;
608 spsr_idx
= MISCREG_SPSR_EL3
;
611 panic("Invalid target exception level");
615 // Save process state into SPSR_ELx
616 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
618 spsr
.nz
= tc
->readCCReg(CCREG_NZ
);
619 spsr
.c
= tc
->readCCReg(CCREG_C
);
620 spsr
.v
= tc
->readCCReg(CCREG_V
);
622 // Force some bitfields to 0
631 spsr
.ge
= tc
->readCCReg(CCREG_GE
);
632 ITSTATE it
= tc
->pcState().itstate();
634 spsr
.it1
= it
.bottom2
;
635 // Force some bitfields to 0
639 tc
->setMiscReg(spsr_idx
, spsr
);
641 // Save preferred return address into ELR_ELx
642 Addr curr_pc
= tc
->pcState().pc();
643 Addr ret_addr
= curr_pc
;
645 ret_addr
+= armPcElrOffset();
647 ret_addr
+= spsr
.t
? thumbPcElrOffset() : armPcElrOffset();
648 tc
->setMiscReg(elr_idx
, ret_addr
);
650 // Update process state
651 OperatingMode64 mode
= 0;
659 tc
->setMiscReg(MISCREG_CPSR
, cpsr
);
661 // Set PC to start of exception handler
662 Addr new_pc
= purifyTaggedAddr(getVector64(tc
), tc
, toEL
);
663 DPRINTF(Faults
, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x "
664 "elr:%#x newVec: %#x\n", name(), cpsr
, curr_pc
, ret_addr
, new_pc
);
666 pc
.aarch64(!cpsr
.width
);
667 pc
.nextAArch64(!cpsr
.width
);
670 // If we have a valid instruction then use it to annotate this fault with
671 // extra information. This is used to generate the correct fault syndrome
674 reinterpret_cast<ArmStaticInst
*>(inst
.get())->annotateFault(this);
675 // Save exception syndrome
676 if ((nextMode() != MODE_IRQ
) && (nextMode() != MODE_FIQ
))
677 setSyndrome(tc
, getSyndromeReg64());
681 Reset::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
684 tc
->getCpuPtr()->clearInterrupts(tc
->threadId());
687 if (!ArmSystem::highestELIs64(tc
)) {
688 ArmFault::invoke(tc
, inst
);
689 tc
->setMiscReg(MISCREG_VMPIDR
,
690 getMPIDR(dynamic_cast<ArmSystem
*>(tc
->getSystemPtr()), tc
));
692 // Unless we have SMC code to get us there, boot in HYP!
693 if (ArmSystem::haveVirtualization(tc
) &&
694 !ArmSystem::haveSecurity(tc
)) {
695 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
696 cpsr
.mode
= MODE_HYP
;
697 tc
->setMiscReg(MISCREG_CPSR
, cpsr
);
700 // Advance the PC to the IMPLEMENTATION DEFINED reset value
701 PCState pc
= ArmSystem::resetAddr64(tc
);
703 pc
.nextAArch64(true);
709 UndefinedInstruction::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
712 ArmFault::invoke(tc
, inst
);
716 // If the mnemonic isn't defined this has to be an unknown instruction.
717 assert(unknown
|| mnemonic
!= NULL
);
719 panic("Attempted to execute disabled instruction "
720 "'%s' (inst 0x%08x)", mnemonic
, machInst
);
721 } else if (unknown
) {
722 panic("Attempted to execute unknown instruction (inst 0x%08x)",
725 panic("Attempted to execute unimplemented instruction "
726 "'%s' (inst 0x%08x)", mnemonic
, machInst
);
731 UndefinedInstruction::routeToHyp(ThreadContext
*tc
) const
735 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
736 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
737 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
739 // if in Hyp mode then stay in Hyp mode
740 toHyp
= scr
.ns
&& (cpsr
.mode
== MODE_HYP
);
741 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
742 toHyp
|= !inSecureState(scr
, cpsr
) && hcr
.tge
&& (cpsr
.mode
== MODE_USER
);
747 UndefinedInstruction::iss() const
749 if (overrideEc
== EC_INVALID
)
752 uint32_t new_iss
= 0;
753 uint32_t op0
, op1
, op2
, CRn
, CRm
, Rt
, dir
;
755 dir
= bits(machInst
, 21, 21);
756 op0
= bits(machInst
, 20, 19);
757 op1
= bits(machInst
, 18, 16);
758 CRn
= bits(machInst
, 15, 12);
759 CRm
= bits(machInst
, 11, 8);
760 op2
= bits(machInst
, 7, 5);
761 Rt
= bits(machInst
, 4, 0);
763 new_iss
= op0
<< 20 | op2
<< 17 | op1
<< 14 | CRn
<< 10 |
764 Rt
<< 5 | CRm
<< 1 | dir
;
770 SupervisorCall::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
773 ArmFault::invoke(tc
, inst
);
777 // As of now, there isn't a 32 bit thumb version of this instruction.
778 assert(!machInst
.bigThumb
);
780 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
781 OperatingMode mode
= (OperatingMode
)(uint8_t)cpsr
.mode
;
782 if (opModeIs64(mode
))
783 callNum
= tc
->readIntReg(INTREG_X8
);
785 callNum
= tc
->readIntReg(INTREG_R7
);
786 tc
->syscall(callNum
);
788 // Advance the PC since that won't happen automatically.
789 PCState pc
= tc
->pcState();
796 SupervisorCall::routeToHyp(ThreadContext
*tc
) const
800 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
801 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
802 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
804 // if in Hyp mode then stay in Hyp mode
805 toHyp
= scr
.ns
&& (cpsr
.mode
== MODE_HYP
);
806 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
807 toHyp
|= !inSecureState(scr
, cpsr
) && hcr
.tge
&& (cpsr
.mode
== MODE_USER
);
812 SupervisorCall::ec(ThreadContext
*tc
) const
814 return (overrideEc
!= EC_INVALID
) ? overrideEc
:
815 (from64
? EC_SVC_64
: vals
.ec
);
819 SupervisorCall::iss() const
821 // Even if we have a 24 bit imm from an arm32 instruction then we only use
822 // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC).
823 return issRaw
& 0xFFFF;
827 SecureMonitorCall::iss() const
830 return bits(machInst
, 20, 5);
835 UndefinedInstruction::ec(ThreadContext
*tc
) const
837 return (overrideEc
!= EC_INVALID
) ? overrideEc
: vals
.ec
;
841 HypervisorCall::HypervisorCall(ExtMachInst _machInst
, uint32_t _imm
) :
842 ArmFaultVals
<HypervisorCall
>(_machInst
, _imm
)
846 HypervisorTrap::ec(ThreadContext
*tc
) const
848 return (overrideEc
!= EC_INVALID
) ? overrideEc
: vals
.ec
;
853 ArmFaultVals
<T
>::offset(ThreadContext
*tc
)
855 bool isHypTrap
= false;
857 // Normally we just use the exception vector from the table at the top if
858 // this file, however if this exception has caused a transition to hype
859 // mode, and its an exception type that would only do this if it has been
860 // trapped then we use the hyp trap vector instead of the normal vector
861 if (vals
.hypTrappable
) {
862 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
863 if (cpsr
.mode
== MODE_HYP
) {
864 CPSR spsr
= tc
->readMiscReg(MISCREG_SPSR_HYP
);
865 isHypTrap
= spsr
.mode
!= MODE_HYP
;
868 return isHypTrap
? 0x14 : vals
.offset
;
872 // SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx)
875 // esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32;
876 // esr.il = !machInst.thumb;
877 // if (machInst.aarch64)
878 // esr.imm16 = bits(machInst.instBits, 20, 5);
879 // else if (machInst.thumb)
880 // esr.imm16 = bits(machInst.instBits, 7, 0);
882 // esr.imm16 = bits(machInst.instBits, 15, 0);
883 // tc->setMiscReg(esr_idx, esr);
887 SecureMonitorCall::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
890 ArmFault::invoke(tc
, inst
);
896 SecureMonitorCall::ec(ThreadContext
*tc
) const
898 return (from64
? EC_SMC_64
: vals
.ec
);
902 SupervisorTrap::ec(ThreadContext
*tc
) const
904 return (overrideEc
!= EC_INVALID
) ? overrideEc
: vals
.ec
;
908 SecureMonitorTrap::ec(ThreadContext
*tc
) const
910 return (overrideEc
!= EC_INVALID
) ? overrideEc
:
911 (from64
? EC_SMC_64
: vals
.ec
);
916 AbortFault
<T
>::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
918 if (tranMethod
== ArmFault::UnknownTran
) {
919 tranMethod
= longDescFormatInUse(tc
) ? ArmFault::LpaeTran
920 : ArmFault::VmsaTran
;
922 if ((tranMethod
== ArmFault::VmsaTran
) && this->routeToMonitor(tc
)) {
923 // See ARM ARM B3-1416
924 bool override_LPAE
= false;
925 TTBCR ttbcr_s
= tc
->readMiscReg(MISCREG_TTBCR_S
);
926 TTBCR M5_VAR_USED ttbcr_ns
= tc
->readMiscReg(MISCREG_TTBCR_NS
);
928 override_LPAE
= true;
930 // Unimplemented code option, not seen in testing. May need
931 // extension according to the manual exceprt above.
932 DPRINTF(Faults
, "Warning: Incomplete translation method "
933 "override detected.\n");
936 tranMethod
= ArmFault::LpaeTran
;
940 if (source
== ArmFault::AsynchronousExternalAbort
) {
941 tc
->getCpuPtr()->clearInterrupt(tc
->threadId(), INT_ABT
, 0);
943 // Get effective fault source encoding
944 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
945 FSR fsr
= getFsr(tc
);
947 // source must be determined BEFORE invoking generic routines which will
948 // try to set hsr etc. and are based upon source!
949 ArmFaultVals
<T
>::invoke(tc
, inst
);
951 if (!this->to64
) { // AArch32
952 if (cpsr
.mode
== MODE_HYP
) {
953 tc
->setMiscReg(T::HFarIndex
, faultAddr
);
955 tc
->setMiscReg(MISCREG_HPFAR
, (faultAddr
>> 8) & ~0xf);
956 tc
->setMiscReg(T::HFarIndex
, OVAddr
);
958 tc
->setMiscReg(T::FsrIndex
, fsr
);
959 tc
->setMiscReg(T::FarIndex
, faultAddr
);
961 DPRINTF(Faults
, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\
962 "tranMethod=%#x\n", source
, fsr
, faultAddr
, tranMethod
);
964 // Set the FAR register. Nothing else to do if we are in AArch64 state
965 // because the syndrome register has already been set inside invoke64()
966 tc
->setMiscReg(AbortFault
<T
>::getFaultAddrReg64(), faultAddr
);
972 AbortFault
<T
>::getFsr(ThreadContext
*tc
)
976 if (((CPSR
) tc
->readMiscRegNoEffect(MISCREG_CPSR
)).width
) {
978 assert(tranMethod
!= ArmFault::UnknownTran
);
979 if (tranMethod
== ArmFault::LpaeTran
) {
980 srcEncoded
= ArmFault::longDescFaultSources
[source
];
981 fsr
.status
= srcEncoded
;
984 srcEncoded
= ArmFault::shortDescFaultSources
[source
];
985 fsr
.fsLow
= bits(srcEncoded
, 3, 0);
986 fsr
.fsHigh
= bits(srcEncoded
, 4);
987 fsr
.domain
= static_cast<uint8_t>(domain
);
989 fsr
.wnr
= (write
? 1 : 0);
993 srcEncoded
= ArmFault::aarch64FaultSources
[source
];
995 if (srcEncoded
== ArmFault::FaultSourceInvalid
) {
996 panic("Invalid fault source\n");
1003 AbortFault
<T
>::abortDisable(ThreadContext
*tc
)
1005 if (ArmSystem::haveSecurity(tc
)) {
1006 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1007 return (!scr
.ns
|| scr
.aw
);
1014 AbortFault
<T
>::annotate(ArmFault::AnnotationIDs id
, uint64_t val
)
1018 case ArmFault::S1PTW
:
1025 // Just ignore unknown ID's
1033 AbortFault
<T
>::iss() const
1037 val
= srcEncoded
& 0x3F;
1045 AbortFault
<T
>::isMMUFault() const
1047 // NOTE: Not relying on LL information being aligned to lowest bits here
1049 (source
== ArmFault::AlignmentFault
) ||
1050 ((source
>= ArmFault::TranslationLL
) &&
1051 (source
< ArmFault::TranslationLL
+ 4)) ||
1052 ((source
>= ArmFault::AccessFlagLL
) &&
1053 (source
< ArmFault::AccessFlagLL
+ 4)) ||
1054 ((source
>= ArmFault::DomainLL
) &&
1055 (source
< ArmFault::DomainLL
+ 4)) ||
1056 ((source
>= ArmFault::PermissionLL
) &&
1057 (source
< ArmFault::PermissionLL
+ 4));
1061 PrefetchAbort::ec(ThreadContext
*tc
) const
1066 return EC_PREFETCH_ABORT_CURR_EL
;
1068 return EC_PREFETCH_ABORT_LOWER_EL
;
1071 // Abort faults have different EC codes depending on whether
1072 // the fault originated within HYP mode, or not. So override
1073 // the method and add the extra adjustment of the EC value.
1075 ExceptionClass ec
= ArmFaultVals
<PrefetchAbort
>::vals
.ec
;
1077 CPSR spsr
= tc
->readMiscReg(MISCREG_SPSR_HYP
);
1078 if (spsr
.mode
== MODE_HYP
) {
1079 ec
= ((ExceptionClass
) (((uint32_t) ec
) + 1));
1086 PrefetchAbort::routeToMonitor(ThreadContext
*tc
) const
1090 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1092 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1094 return scr
.ea
&& !isMMUFault();
1098 PrefetchAbort::routeToHyp(ThreadContext
*tc
) const
1102 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1103 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
1104 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
1105 HDCR hdcr
= tc
->readMiscRegNoEffect(MISCREG_HDCR
);
1107 // if in Hyp mode then stay in Hyp mode
1108 toHyp
= scr
.ns
&& (cpsr
.mode
== MODE_HYP
);
1109 // otherwise, check whether to take to Hyp mode through Hyp Trap vector
1111 ( (source
== DebugEvent
) && hdcr
.tde
&& (cpsr
.mode
!= MODE_HYP
)) ||
1112 ( (source
== SynchronousExternalAbort
) && hcr
.tge
&& (cpsr
.mode
== MODE_USER
))
1113 ) && !inSecureState(scr
, cpsr
);
1118 DataAbort::ec(ThreadContext
*tc
) const
1122 if (source
== ArmFault::AsynchronousExternalAbort
) {
1123 panic("Asynchronous External Abort should be handled with "
1124 "SystemErrors (SErrors)!");
1127 return EC_DATA_ABORT_CURR_EL
;
1129 return EC_DATA_ABORT_LOWER_EL
;
1132 // Abort faults have different EC codes depending on whether
1133 // the fault originated within HYP mode, or not. So override
1134 // the method and add the extra adjustment of the EC value.
1136 ExceptionClass ec
= ArmFaultVals
<DataAbort
>::vals
.ec
;
1138 CPSR spsr
= tc
->readMiscReg(MISCREG_SPSR_HYP
);
1139 if (spsr
.mode
== MODE_HYP
) {
1140 ec
= ((ExceptionClass
) (((uint32_t) ec
) + 1));
1147 DataAbort::routeToMonitor(ThreadContext
*tc
) const
1151 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1153 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1155 return scr
.ea
&& !isMMUFault();
1159 DataAbort::routeToHyp(ThreadContext
*tc
) const
1163 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1164 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
1165 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
1166 HDCR hdcr
= tc
->readMiscRegNoEffect(MISCREG_HDCR
);
1168 // if in Hyp mode then stay in Hyp mode
1169 toHyp
= scr
.ns
&& (cpsr
.mode
== MODE_HYP
);
1170 // otherwise, check whether to take to Hyp mode through Hyp Trap vector
1172 ( (cpsr
.mode
!= MODE_HYP
) && ( ((source
== AsynchronousExternalAbort
) && hcr
.amo
) ||
1173 ((source
== DebugEvent
) && hdcr
.tde
) )
1175 ( (cpsr
.mode
== MODE_USER
) && hcr
.tge
&&
1176 ((source
== AlignmentFault
) ||
1177 (source
== SynchronousExternalAbort
))
1179 ) && !inSecureState(scr
, cpsr
);
1184 DataAbort::iss() const
1188 // Add on the data abort specific fields to the generic abort ISS value
1189 val
= AbortFault
<DataAbort
>::iss();
1190 // ISS is valid if not caused by a stage 1 page table walk, and when taken
1191 // to AArch64 only when directed to EL2
1192 if (!s1ptw
&& (!to64
|| toEL
== EL2
)) {
1198 // AArch64 only. These assignments are safe on AArch32 as well
1199 // because these vars are initialized to false
1208 DataAbort::annotate(AnnotationIDs id
, uint64_t val
)
1210 AbortFault
<DataAbort
>::annotate(id
, val
);
1233 // Just ignore unknown ID's
1240 VirtualDataAbort::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
1242 AbortFault
<VirtualDataAbort
>::invoke(tc
, inst
);
1243 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
1245 tc
->setMiscRegNoEffect(MISCREG_HCR
, hcr
);
1249 Interrupt::routeToMonitor(ThreadContext
*tc
) const
1251 assert(ArmSystem::haveSecurity(tc
));
1254 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1256 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1261 Interrupt::routeToHyp(ThreadContext
*tc
) const
1265 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1266 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
1267 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
1268 // Determine whether IRQs are routed to Hyp mode.
1269 toHyp
= (!scr
.irq
&& hcr
.imo
&& !inSecureState(scr
, cpsr
)) ||
1270 (cpsr
.mode
== MODE_HYP
);
1275 Interrupt::abortDisable(ThreadContext
*tc
)
1277 if (ArmSystem::haveSecurity(tc
)) {
1278 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1279 return (!scr
.ns
|| scr
.aw
);
1284 VirtualInterrupt::VirtualInterrupt()
1288 FastInterrupt::routeToMonitor(ThreadContext
*tc
) const
1290 assert(ArmSystem::haveSecurity(tc
));
1293 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1295 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1300 FastInterrupt::routeToHyp(ThreadContext
*tc
) const
1304 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1305 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
1306 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
1307 // Determine whether IRQs are routed to Hyp mode.
1308 toHyp
= (!scr
.fiq
&& hcr
.fmo
&& !inSecureState(scr
, cpsr
)) ||
1309 (cpsr
.mode
== MODE_HYP
);
1314 FastInterrupt::abortDisable(ThreadContext
*tc
)
1316 if (ArmSystem::haveSecurity(tc
)) {
1317 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1318 return (!scr
.ns
|| scr
.aw
);
1324 FastInterrupt::fiqDisable(ThreadContext
*tc
)
1326 if (ArmSystem::haveVirtualization(tc
)) {
1328 } else if (ArmSystem::haveSecurity(tc
)) {
1329 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1330 return (!scr
.ns
|| scr
.fw
);
1335 VirtualFastInterrupt::VirtualFastInterrupt()
1339 PCAlignmentFault::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
1341 ArmFaultVals
<PCAlignmentFault
>::invoke(tc
, inst
);
1344 tc
->setMiscReg(getFaultAddrReg64(), faultPC
);
1347 SPAlignmentFault::SPAlignmentFault()
1350 SystemError::SystemError()
1354 SystemError::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
1356 tc
->getCpuPtr()->clearInterrupt(tc
->threadId(), INT_ABT
, 0);
1357 ArmFault::invoke(tc
, inst
);
1361 SystemError::routeToMonitor(ThreadContext
*tc
) const
1363 assert(ArmSystem::haveSecurity(tc
));
1365 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1370 SystemError::routeToHyp(ThreadContext
*tc
) const
1375 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1376 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
1377 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
1379 toHyp
= (!scr
.ea
&& hcr
.amo
&& !inSecureState(scr
, cpsr
)) ||
1380 (!scr
.ea
&& !scr
.rw
&& !hcr
.amo
&& !inSecureState(scr
,cpsr
));
1385 FlushPipe::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
) {
1386 DPRINTF(Faults
, "Invoking FlushPipe Fault\n");
1388 // Set the PC to the next instruction of the faulting instruction.
1389 // Net effect is simply squashing all instructions behind and
1390 // start refetching from the next instruction.
1391 PCState pc
= tc
->pcState();
1393 inst
->advancePC(pc
);
1398 ArmSev::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
) {
1399 DPRINTF(Faults
, "Invoking ArmSev Fault\n");
1403 // Set sev_mailbox to 1, clear the pending interrupt from remote
1404 // SEV execution and let pipeline continue as pcState is still
1406 tc
->setMiscReg(MISCREG_SEV_MAILBOX
, 1);
1407 tc
->getCpuPtr()->clearInterrupt(tc
->threadId(), INT_SEV
, 0);
1410 // Instantiate all the templates to make the linker happy
1411 template class ArmFaultVals
<Reset
>;
1412 template class ArmFaultVals
<UndefinedInstruction
>;
1413 template class ArmFaultVals
<SupervisorCall
>;
1414 template class ArmFaultVals
<SecureMonitorCall
>;
1415 template class ArmFaultVals
<HypervisorCall
>;
1416 template class ArmFaultVals
<PrefetchAbort
>;
1417 template class ArmFaultVals
<DataAbort
>;
1418 template class ArmFaultVals
<VirtualDataAbort
>;
1419 template class ArmFaultVals
<HypervisorTrap
>;
1420 template class ArmFaultVals
<Interrupt
>;
1421 template class ArmFaultVals
<VirtualInterrupt
>;
1422 template class ArmFaultVals
<FastInterrupt
>;
1423 template class ArmFaultVals
<VirtualFastInterrupt
>;
1424 template class ArmFaultVals
<SupervisorTrap
>;
1425 template class ArmFaultVals
<SecureMonitorTrap
>;
1426 template class ArmFaultVals
<PCAlignmentFault
>;
1427 template class ArmFaultVals
<SPAlignmentFault
>;
1428 template class ArmFaultVals
<SystemError
>;
1429 template class ArmFaultVals
<FlushPipe
>;
1430 template class ArmFaultVals
<ArmSev
>;
1431 template class AbortFault
<PrefetchAbort
>;
1432 template class AbortFault
<DataAbort
>;
1433 template class AbortFault
<VirtualDataAbort
>;
1436 IllegalInstSetStateFault::IllegalInstSetStateFault()
1440 } // namespace ArmISA