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15 * Copyright (c) 2007-2008 The Florida State University
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47 #include "arch/arm/faults.hh"
49 #include "arch/arm/insts/static_inst.hh"
50 #include "arch/arm/system.hh"
51 #include "arch/arm/utility.hh"
52 #include "base/compiler.hh"
53 #include "base/trace.hh"
54 #include "cpu/base.hh"
55 #include "cpu/thread_context.hh"
56 #include "debug/Faults.hh"
57 #include "sim/full_system.hh"
62 uint8_t ArmFault::shortDescFaultSources
[] = {
63 0x01, // AlignmentFault
64 0x04, // InstructionCacheMaintenance
65 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID)
66 0x0c, // SynchExtAbtOnTranslTableWalkL1
67 0x0e, // SynchExtAbtOnTranslTableWalkL2
68 0xff, // SynchExtAbtOnTranslTableWalkL3 (INVALID)
69 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID)
70 0x1c, // SynchPtyErrOnTranslTableWalkL1
71 0x1e, // SynchPtyErrOnTranslTableWalkL2
72 0xff, // SynchPtyErrOnTranslTableWalkL3 (INVALID)
73 0xff, // TranslationL0 (INVALID)
74 0x05, // TranslationL1
75 0x07, // TranslationL2
76 0xff, // TranslationL3 (INVALID)
77 0xff, // AccessFlagL0 (INVALID)
80 0xff, // AccessFlagL3 (INVALID)
81 0xff, // DomainL0 (INVALID)
84 0xff, // DomainL3 (INVALID)
85 0xff, // PermissionL0 (INVALID)
88 0xff, // PermissionL3 (INVALID)
90 0x08, // SynchronousExternalAbort
91 0x10, // TLBConflictAbort
92 0x19, // SynchPtyErrOnMemoryAccess
93 0x16, // AsynchronousExternalAbort
94 0x18, // AsynchPtyErrOnMemoryAccess
95 0xff, // AddressSizeL0 (INVALID)
96 0xff, // AddressSizeL1 (INVALID)
97 0xff, // AddressSizeL2 (INVALID)
98 0xff, // AddressSizeL3 (INVALID)
99 0x40, // PrefetchTLBMiss
100 0x80 // PrefetchUncacheable
103 static_assert(sizeof(ArmFault::shortDescFaultSources
) ==
104 ArmFault::NumFaultSources
,
105 "Invalid size of ArmFault::shortDescFaultSources[]");
107 uint8_t ArmFault::longDescFaultSources
[] = {
108 0x21, // AlignmentFault
109 0xff, // InstructionCacheMaintenance (INVALID)
110 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID)
111 0x15, // SynchExtAbtOnTranslTableWalkL1
112 0x16, // SynchExtAbtOnTranslTableWalkL2
113 0x17, // SynchExtAbtOnTranslTableWalkL3
114 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID)
115 0x1d, // SynchPtyErrOnTranslTableWalkL1
116 0x1e, // SynchPtyErrOnTranslTableWalkL2
117 0x1f, // SynchPtyErrOnTranslTableWalkL3
118 0xff, // TranslationL0 (INVALID)
119 0x05, // TranslationL1
120 0x06, // TranslationL2
121 0x07, // TranslationL3
122 0xff, // AccessFlagL0 (INVALID)
123 0x09, // AccessFlagL1
124 0x0a, // AccessFlagL2
125 0x0b, // AccessFlagL3
126 0xff, // DomainL0 (INVALID)
129 0xff, // DomainL3 (RESERVED)
130 0xff, // PermissionL0 (INVALID)
131 0x0d, // PermissionL1
132 0x0e, // PermissionL2
133 0x0f, // PermissionL3
135 0x10, // SynchronousExternalAbort
136 0x30, // TLBConflictAbort
137 0x18, // SynchPtyErrOnMemoryAccess
138 0x11, // AsynchronousExternalAbort
139 0x19, // AsynchPtyErrOnMemoryAccess
140 0xff, // AddressSizeL0 (INVALID)
141 0xff, // AddressSizeL1 (INVALID)
142 0xff, // AddressSizeL2 (INVALID)
143 0xff, // AddressSizeL3 (INVALID)
144 0x40, // PrefetchTLBMiss
145 0x80 // PrefetchUncacheable
148 static_assert(sizeof(ArmFault::longDescFaultSources
) ==
149 ArmFault::NumFaultSources
,
150 "Invalid size of ArmFault::longDescFaultSources[]");
152 uint8_t ArmFault::aarch64FaultSources
[] = {
153 0x21, // AlignmentFault
154 0xff, // InstructionCacheMaintenance (INVALID)
155 0x14, // SynchExtAbtOnTranslTableWalkL0
156 0x15, // SynchExtAbtOnTranslTableWalkL1
157 0x16, // SynchExtAbtOnTranslTableWalkL2
158 0x17, // SynchExtAbtOnTranslTableWalkL3
159 0x1c, // SynchPtyErrOnTranslTableWalkL0
160 0x1d, // SynchPtyErrOnTranslTableWalkL1
161 0x1e, // SynchPtyErrOnTranslTableWalkL2
162 0x1f, // SynchPtyErrOnTranslTableWalkL3
163 0x04, // TranslationL0
164 0x05, // TranslationL1
165 0x06, // TranslationL2
166 0x07, // TranslationL3
167 0x08, // AccessFlagL0
168 0x09, // AccessFlagL1
169 0x0a, // AccessFlagL2
170 0x0b, // AccessFlagL3
171 // @todo: Section & Page Domain Fault in AArch64?
172 0xff, // DomainL0 (INVALID)
173 0xff, // DomainL1 (INVALID)
174 0xff, // DomainL2 (INVALID)
175 0xff, // DomainL3 (INVALID)
176 0x0c, // PermissionL0
177 0x0d, // PermissionL1
178 0x0e, // PermissionL2
179 0x0f, // PermissionL3
181 0x10, // SynchronousExternalAbort
182 0x30, // TLBConflictAbort
183 0x18, // SynchPtyErrOnMemoryAccess
184 0xff, // AsynchronousExternalAbort (INVALID)
185 0xff, // AsynchPtyErrOnMemoryAccess (INVALID)
186 0x00, // AddressSizeL0
187 0x01, // AddressSizeL1
188 0x02, // AddressSizeL2
189 0x03, // AddressSizeL3
190 0x40, // PrefetchTLBMiss
191 0x80 // PrefetchUncacheable
194 static_assert(sizeof(ArmFault::aarch64FaultSources
) ==
195 ArmFault::NumFaultSources
,
196 "Invalid size of ArmFault::aarch64FaultSources[]");
198 // Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode,
199 // {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap,
200 // {A, F} disable, class, stat
201 template<> ArmFault::FaultVals ArmFaultVals
<Reset
>::vals(
202 // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED
203 // location in AArch64)
204 "Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC
,
205 0, 0, 0, 0, false, true, true, EC_UNKNOWN
207 template<> ArmFault::FaultVals ArmFaultVals
<UndefinedInstruction
>::vals(
208 "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED
,
209 4, 2, 0, 0, true, false, false, EC_UNKNOWN
211 template<> ArmFault::FaultVals ArmFaultVals
<SupervisorCall
>::vals(
212 "Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC
,
213 4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP
215 template<> ArmFault::FaultVals ArmFaultVals
<SecureMonitorCall
>::vals(
216 "Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON
,
217 4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP
219 template<> ArmFault::FaultVals ArmFaultVals
<HypervisorCall
>::vals(
220 "Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP
,
221 4, 4, 4, 4, true, false, false, EC_HVC
223 template<> ArmFault::FaultVals ArmFaultVals
<PrefetchAbort
>::vals(
224 "Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT
,
225 4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP
227 template<> ArmFault::FaultVals ArmFaultVals
<DataAbort
>::vals(
228 "Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT
,
229 8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP
231 template<> ArmFault::FaultVals ArmFaultVals
<VirtualDataAbort
>::vals(
232 "Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT
,
233 8, 8, 0, 0, true, true, false, EC_INVALID
235 template<> ArmFault::FaultVals ArmFaultVals
<HypervisorTrap
>::vals(
236 // @todo: double check these values
237 "Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP
,
238 0, 0, 0, 0, false, false, false, EC_UNKNOWN
240 template<> ArmFault::FaultVals ArmFaultVals
<SecureMonitorTrap
>::vals(
241 "Secure Monitor Trap", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON
,
242 4, 2, 0, 0, false, false, false, EC_UNKNOWN
244 template<> ArmFault::FaultVals ArmFaultVals
<Interrupt
>::vals(
245 "IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ
,
246 4, 4, 0, 0, false, true, false, EC_UNKNOWN
248 template<> ArmFault::FaultVals ArmFaultVals
<VirtualInterrupt
>::vals(
249 "Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ
,
250 4, 4, 0, 0, false, true, false, EC_INVALID
252 template<> ArmFault::FaultVals ArmFaultVals
<FastInterrupt
>::vals(
253 "FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ
,
254 4, 4, 0, 0, false, true, true, EC_UNKNOWN
256 template<> ArmFault::FaultVals ArmFaultVals
<VirtualFastInterrupt
>::vals(
257 "Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ
,
258 4, 4, 0, 0, false, true, true, EC_INVALID
260 template<> ArmFault::FaultVals ArmFaultVals
<IllegalInstSetStateFault
>::vals(
261 "Illegal Inst Set State Fault", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED
,
262 4, 2, 0, 0, true, false, false, EC_ILLEGAL_INST
264 template<> ArmFault::FaultVals ArmFaultVals
<SupervisorTrap
>::vals(
265 // Some dummy values (SupervisorTrap is AArch64-only)
266 "Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC
,
267 0, 0, 0, 0, false, false, false, EC_UNKNOWN
269 template<> ArmFault::FaultVals ArmFaultVals
<PCAlignmentFault
>::vals(
270 // Some dummy values (PCAlignmentFault is AArch64-only)
271 "PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC
,
272 0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT
274 template<> ArmFault::FaultVals ArmFaultVals
<SPAlignmentFault
>::vals(
275 // Some dummy values (SPAlignmentFault is AArch64-only)
276 "SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC
,
277 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT
279 template<> ArmFault::FaultVals ArmFaultVals
<SystemError
>::vals(
280 // Some dummy values (SError is AArch64-only)
281 "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC
,
282 0, 0, 0, 0, false, true, true, EC_SERROR
284 template<> ArmFault::FaultVals ArmFaultVals
<SoftwareBreakpoint
>::vals(
285 // Some dummy values (SoftwareBreakpoint is AArch64-only)
286 "Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC
,
287 0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT
289 template<> ArmFault::FaultVals ArmFaultVals
<ArmSev
>::vals(
291 "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC
,
292 0, 0, 0, 0, false, true, true, EC_UNKNOWN
296 ArmFault::getVector(ThreadContext
*tc
)
300 // Check for invalid modes
301 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
302 assert(ArmSystem::haveSecurity(tc
) || cpsr
.mode
!= MODE_MON
);
303 assert(ArmSystem::haveVirtualization(tc
) || cpsr
.mode
!= MODE_HYP
);
308 base
= tc
->readMiscReg(MISCREG_MVBAR
);
311 base
= tc
->readMiscReg(MISCREG_HVBAR
);
314 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR
);
318 base
= ArmSystem::haveSecurity(tc
) ?
319 tc
->readMiscReg(MISCREG_VBAR
) : 0;
324 return base
+ offset(tc
);
328 ArmFault::getVector64(ThreadContext
*tc
)
333 assert(ArmSystem::haveSecurity(tc
));
334 vbar
= tc
->readMiscReg(MISCREG_VBAR_EL3
);
337 assert(ArmSystem::haveVirtualization(tc
));
338 vbar
= tc
->readMiscReg(MISCREG_VBAR_EL2
);
341 vbar
= tc
->readMiscReg(MISCREG_VBAR_EL1
);
344 panic("Invalid target exception level");
347 return vbar
+ offset64(tc
);
351 ArmFault::getSyndromeReg64() const
355 return MISCREG_ESR_EL1
;
357 return MISCREG_ESR_EL2
;
359 return MISCREG_ESR_EL3
;
361 panic("Invalid exception level");
367 ArmFault::getFaultAddrReg64() const
371 return MISCREG_FAR_EL1
;
373 return MISCREG_FAR_EL2
;
375 return MISCREG_FAR_EL3
;
377 panic("Invalid exception level");
383 ArmFault::setSyndrome(ThreadContext
*tc
, MiscRegIndex syndrome_reg
)
386 uint32_t exc_class
= (uint32_t) ec(tc
);
387 uint32_t issVal
= iss();
389 assert(!from64
|| ArmSystem::highestELIs64(tc
));
391 value
= exc_class
<< 26;
393 // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24,
394 // 0x25) for which the ISS information is not valid (ARMv7).
395 // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not
396 // valid it is treated as RES1.
399 } else if ((bits(exc_class
, 5, 3) != 4) ||
400 (bits(exc_class
, 2) && bits(issVal
, 24))) {
401 if (!machInst
.thumb
|| machInst
.bigThumb
)
404 // Condition code valid for EC[5:4] nonzero
405 if (!from64
&& ((bits(exc_class
, 5, 4) == 0) &&
406 (bits(exc_class
, 3, 0) != 0))) {
407 if (!machInst
.thumb
) {
409 ConditionCode condCode
= (ConditionCode
) (uint32_t) machInst
.condCode
;
410 // If its on unconditional instruction report with a cond code of
411 // 0xE, ie the unconditional code
412 cond
= (condCode
== COND_UC
) ? COND_AL
: condCode
;
416 value
|= bits(issVal
, 19, 0);
420 tc
->setMiscReg(syndrome_reg
, value
);
424 ArmFault::update(ThreadContext
*tc
)
426 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
428 // Determine source exception level and mode
429 fromMode
= (OperatingMode
) (uint8_t) cpsr
.mode
;
430 fromEL
= opModeToEL(fromMode
);
431 if (opModeIs64(fromMode
))
434 // Determine target exception level (aarch64) or target execution
436 if (ArmSystem::haveSecurity(tc
) && routeToMonitor(tc
)) {
439 } else if (ArmSystem::haveVirtualization(tc
) && routeToHyp(tc
)) {
445 toEL
= opModeToEL(toMode
);
451 // Check for Set Priviledge Access Never, if PAN is supported
452 AA64MMFR1 mmfr1
= tc
->readMiscReg(MISCREG_ID_AA64MMFR1_EL1
);
455 const SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL1
);
459 const HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR_EL2
);
460 if (toEL
== EL2
&& hcr
.e2h
&& hcr
.tge
) {
461 const SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR_EL2
);
466 to64
= ELIs64(tc
, toEL
);
468 // The fault specific informations have been updated; it is
469 // now possible to use them inside the fault.
474 ArmFault::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
477 // Update fault state informations, like the starting mode (aarch32)
478 // or EL (aarch64) and the ending mode or EL.
479 // From the update function we are also evaluating if the fault must
480 // be handled in AArch64 mode (to64).
484 // Invoke exception handler in AArch64 state
489 // ARMv7 (ARM ARM issue C B1.9)
491 bool have_security
= ArmSystem::haveSecurity(tc
);
493 FaultBase::invoke(tc
);
498 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR
);
499 SCR scr
= tc
->readMiscReg(MISCREG_SCR
);
500 CPSR saved_cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
501 saved_cpsr
.nz
= tc
->readCCReg(CCREG_NZ
);
502 saved_cpsr
.c
= tc
->readCCReg(CCREG_C
);
503 saved_cpsr
.v
= tc
->readCCReg(CCREG_V
);
504 saved_cpsr
.ge
= tc
->readCCReg(CCREG_GE
);
506 Addr curPc M5_VAR_USED
= tc
->pcState().pc();
507 ITSTATE it
= tc
->pcState().itstate();
508 saved_cpsr
.it2
= it
.top6
;
509 saved_cpsr
.it1
= it
.bottom2
;
511 // if we have a valid instruction then use it to annotate this fault with
512 // extra information. This is used to generate the correct fault syndrome
514 ArmStaticInst
*arm_inst M5_VAR_USED
= instrAnnotate(inst
);
516 // Ensure Secure state if initially in Monitor mode
517 if (have_security
&& saved_cpsr
.mode
== MODE_MON
) {
518 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
521 tc
->setMiscRegNoEffect(MISCREG_SCR
, scr
);
525 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
528 // some bits are set differently if we have been routed to hyp mode
529 if (cpsr
.mode
== MODE_HYP
) {
530 SCTLR hsctlr
= tc
->readMiscReg(MISCREG_HSCTLR
);
533 if (!scr
.ea
) {cpsr
.a
= 1;}
534 if (!scr
.fiq
) {cpsr
.f
= 1;}
535 if (!scr
.irq
) {cpsr
.i
= 1;}
536 } else if (cpsr
.mode
== MODE_MON
) {
537 // Special case handling when entering monitor mode
547 // The *Disable functions are virtual and different per fault
548 cpsr
.a
= cpsr
.a
| abortDisable(tc
);
549 cpsr
.f
= cpsr
.f
| fiqDisable(tc
);
552 cpsr
.it1
= cpsr
.it2
= 0;
554 cpsr
.pan
= span
? 1 : saved_cpsr
.pan
;
555 tc
->setMiscReg(MISCREG_CPSR
, cpsr
);
557 // Make sure mailbox sets to one always
558 tc
->setMiscReg(MISCREG_SEV_MAILBOX
, 1);
560 // Clear the exclusive monitor
561 tc
->setMiscReg(MISCREG_LOCKFLAG
, 0);
563 if (cpsr
.mode
== MODE_HYP
) {
564 tc
->setMiscReg(MISCREG_ELR_HYP
, curPc
+
565 (saved_cpsr
.t
? thumbPcOffset(true) : armPcOffset(true)));
567 tc
->setIntReg(INTREG_LR
, curPc
+
568 (saved_cpsr
.t
? thumbPcOffset(false) : armPcOffset(false)));
573 tc
->setMiscReg(MISCREG_SPSR_FIQ
, saved_cpsr
);
576 tc
->setMiscReg(MISCREG_SPSR_IRQ
, saved_cpsr
);
579 tc
->setMiscReg(MISCREG_SPSR_SVC
, saved_cpsr
);
582 assert(have_security
);
583 tc
->setMiscReg(MISCREG_SPSR_MON
, saved_cpsr
);
586 tc
->setMiscReg(MISCREG_SPSR_ABT
, saved_cpsr
);
589 tc
->setMiscReg(MISCREG_SPSR_UND
, saved_cpsr
);
590 if (ec(tc
) != EC_UNKNOWN
)
591 setSyndrome(tc
, MISCREG_HSR
);
594 assert(ArmSystem::haveVirtualization(tc
));
595 tc
->setMiscReg(MISCREG_SPSR_HYP
, saved_cpsr
);
596 setSyndrome(tc
, MISCREG_HSR
);
599 panic("unknown Mode\n");
602 Addr newPc
= getVector(tc
);
603 DPRINTF(Faults
, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x "
604 "%s\n", name(), cpsr
, curPc
, tc
->readIntReg(INTREG_LR
),
605 newPc
, arm_inst
? csprintf("inst: %#x", arm_inst
->encoding()) :
609 pc
.nextThumb(pc
.thumb());
611 pc
.nextJazelle(pc
.jazelle());
612 pc
.aarch64(!cpsr
.width
);
613 pc
.nextAArch64(!cpsr
.width
);
614 pc
.illegalExec(false);
619 ArmFault::invoke64(ThreadContext
*tc
, const StaticInstPtr
&inst
)
621 // Determine actual misc. register indices for ELR_ELx and SPSR_ELx
622 MiscRegIndex elr_idx
, spsr_idx
;
625 elr_idx
= MISCREG_ELR_EL1
;
626 spsr_idx
= MISCREG_SPSR_EL1
;
629 assert(ArmSystem::haveVirtualization(tc
));
630 elr_idx
= MISCREG_ELR_EL2
;
631 spsr_idx
= MISCREG_SPSR_EL2
;
634 assert(ArmSystem::haveSecurity(tc
));
635 elr_idx
= MISCREG_ELR_EL3
;
636 spsr_idx
= MISCREG_SPSR_EL3
;
639 panic("Invalid target exception level");
643 // Save process state into SPSR_ELx
644 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
646 spsr
.nz
= tc
->readCCReg(CCREG_NZ
);
647 spsr
.c
= tc
->readCCReg(CCREG_C
);
648 spsr
.v
= tc
->readCCReg(CCREG_V
);
650 // Force some bitfields to 0
658 spsr
.ge
= tc
->readCCReg(CCREG_GE
);
659 ITSTATE it
= tc
->pcState().itstate();
661 spsr
.it1
= it
.bottom2
;
662 // Force some bitfields to 0
665 tc
->setMiscReg(spsr_idx
, spsr
);
667 // Save preferred return address into ELR_ELx
668 Addr curr_pc
= tc
->pcState().pc();
669 Addr ret_addr
= curr_pc
;
671 ret_addr
+= armPcElrOffset();
673 ret_addr
+= spsr
.t
? thumbPcElrOffset() : armPcElrOffset();
674 tc
->setMiscReg(elr_idx
, ret_addr
);
676 Addr vec_address
= getVector64(tc
);
678 // Update process state
679 OperatingMode64 mode
= 0;
687 cpsr
.pan
= span
? 1 : spsr
.pan
;
688 tc
->setMiscReg(MISCREG_CPSR
, cpsr
);
690 // If we have a valid instruction then use it to annotate this fault with
691 // extra information. This is used to generate the correct fault syndrome
693 ArmStaticInst
*arm_inst M5_VAR_USED
= instrAnnotate(inst
);
695 // Set PC to start of exception handler
696 Addr new_pc
= purifyTaggedAddr(vec_address
, tc
, toEL
);
697 DPRINTF(Faults
, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x "
698 "elr:%#x newVec: %#x %s\n", name(), cpsr
, curr_pc
, ret_addr
,
699 new_pc
, arm_inst
? csprintf("inst: %#x", arm_inst
->encoding()) :
702 pc
.aarch64(!cpsr
.width
);
703 pc
.nextAArch64(!cpsr
.width
);
704 pc
.illegalExec(false);
707 // Save exception syndrome
708 if ((nextMode() != MODE_IRQ
) && (nextMode() != MODE_FIQ
))
709 setSyndrome(tc
, getSyndromeReg64());
713 ArmFault::instrAnnotate(const StaticInstPtr
&inst
)
716 auto arm_inst
= static_cast<ArmStaticInst
*>(inst
.get());
717 arm_inst
->annotateFault(this);
725 Reset::getVector(ThreadContext
*tc
)
729 // Check for invalid modes
730 CPSR M5_VAR_USED cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
731 assert(ArmSystem::haveSecurity(tc
) || cpsr
.mode
!= MODE_MON
);
732 assert(ArmSystem::haveVirtualization(tc
) || cpsr
.mode
!= MODE_HYP
);
734 // RVBAR is aliased (implemented as) MVBAR in gem5, since the two
735 // are mutually exclusive; there is no need to check here for
736 // which register to use since they hold the same value
737 base
= tc
->readMiscReg(MISCREG_MVBAR
);
739 return base
+ offset(tc
);
743 Reset::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
746 tc
->getCpuPtr()->clearInterrupts(tc
->threadId());
749 if (!ArmSystem::highestELIs64(tc
)) {
750 ArmFault::invoke(tc
, inst
);
751 tc
->setMiscReg(MISCREG_VMPIDR
,
752 getMPIDR(dynamic_cast<ArmSystem
*>(tc
->getSystemPtr()), tc
));
754 // Unless we have SMC code to get us there, boot in HYP!
755 if (ArmSystem::haveVirtualization(tc
) &&
756 !ArmSystem::haveSecurity(tc
)) {
757 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
758 cpsr
.mode
= MODE_HYP
;
759 tc
->setMiscReg(MISCREG_CPSR
, cpsr
);
762 // Advance the PC to the IMPLEMENTATION DEFINED reset value
763 PCState pc
= ArmSystem::resetAddr(tc
);
765 pc
.nextAArch64(true);
771 UndefinedInstruction::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
774 ArmFault::invoke(tc
, inst
);
778 // If the mnemonic isn't defined this has to be an unknown instruction.
779 assert(unknown
|| mnemonic
!= NULL
);
780 auto arm_inst
= static_cast<ArmStaticInst
*>(inst
.get());
782 panic("Attempted to execute disabled instruction "
783 "'%s' (inst 0x%08x)", mnemonic
, arm_inst
->encoding());
784 } else if (unknown
) {
785 panic("Attempted to execute unknown instruction (inst 0x%08x)",
786 arm_inst
->encoding());
788 panic("Attempted to execute unimplemented instruction "
789 "'%s' (inst 0x%08x)", mnemonic
, arm_inst
->encoding());
794 UndefinedInstruction::routeToHyp(ThreadContext
*tc
) const
798 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
799 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
800 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
802 // if in Hyp mode then stay in Hyp mode
803 toHyp
= scr
.ns
&& (currEL(tc
) == EL2
);
804 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
805 toHyp
|= !inSecureState(scr
, cpsr
) && hcr
.tge
&& (currEL(tc
) == EL0
);
810 UndefinedInstruction::iss() const
813 // If UndefinedInstruction is routed to hypervisor, iss field is 0.
818 if (overrideEc
== EC_INVALID
)
821 uint32_t new_iss
= 0;
822 uint32_t op0
, op1
, op2
, CRn
, CRm
, Rt
, dir
;
824 dir
= bits(machInst
, 21, 21);
825 op0
= bits(machInst
, 20, 19);
826 op1
= bits(machInst
, 18, 16);
827 CRn
= bits(machInst
, 15, 12);
828 CRm
= bits(machInst
, 11, 8);
829 op2
= bits(machInst
, 7, 5);
830 Rt
= bits(machInst
, 4, 0);
832 new_iss
= op0
<< 20 | op2
<< 17 | op1
<< 14 | CRn
<< 10 |
833 Rt
<< 5 | CRm
<< 1 | dir
;
839 SupervisorCall::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
842 ArmFault::invoke(tc
, inst
);
846 // As of now, there isn't a 32 bit thumb version of this instruction.
847 assert(!machInst
.bigThumb
);
851 // Advance the PC since that won't happen automatically.
852 PCState pc
= tc
->pcState();
859 SupervisorCall::routeToHyp(ThreadContext
*tc
) const
863 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
864 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
865 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
867 // if in Hyp mode then stay in Hyp mode
868 toHyp
= scr
.ns
&& (cpsr
.mode
== MODE_HYP
);
869 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
870 toHyp
|= !inSecureState(scr
, cpsr
) && hcr
.tge
&& (currEL(tc
) == EL0
);
875 SupervisorCall::ec(ThreadContext
*tc
) const
877 return (overrideEc
!= EC_INVALID
) ? overrideEc
:
878 (from64
? EC_SVC_64
: vals
.ec
);
882 SupervisorCall::iss() const
884 // Even if we have a 24 bit imm from an arm32 instruction then we only use
885 // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC).
886 return issRaw
& 0xFFFF;
890 SecureMonitorCall::iss() const
893 return bits(machInst
, 20, 5);
898 UndefinedInstruction::ec(ThreadContext
*tc
) const
900 // If UndefinedInstruction is routed to hypervisor,
901 // HSR.EC field is 0.
905 return (overrideEc
!= EC_INVALID
) ? overrideEc
: vals
.ec
;
909 HypervisorCall::HypervisorCall(ExtMachInst _machInst
, uint32_t _imm
) :
910 ArmFaultVals
<HypervisorCall
>(_machInst
, _imm
)
914 HypervisorCall::ec(ThreadContext
*tc
) const
916 return from64
? EC_HVC_64
: vals
.ec
;
920 HypervisorTrap::ec(ThreadContext
*tc
) const
922 return (overrideEc
!= EC_INVALID
) ? overrideEc
: vals
.ec
;
927 ArmFaultVals
<T
>::offset(ThreadContext
*tc
)
929 bool isHypTrap
= false;
931 // Normally we just use the exception vector from the table at the top if
932 // this file, however if this exception has caused a transition to hype
933 // mode, and its an exception type that would only do this if it has been
934 // trapped then we use the hyp trap vector instead of the normal vector
935 if (vals
.hypTrappable
) {
936 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
937 if (cpsr
.mode
== MODE_HYP
) {
938 CPSR spsr
= tc
->readMiscReg(MISCREG_SPSR_HYP
);
939 isHypTrap
= spsr
.mode
!= MODE_HYP
;
942 return isHypTrap
? 0x14 : vals
.offset
;
947 ArmFaultVals
<T
>::offset64(ThreadContext
*tc
)
949 if (toEL
== fromEL
) {
950 if (opModeIsT(fromMode
))
951 return vals
.currELTOffset
;
952 return vals
.currELHOffset
;
954 bool lower_32
= false;
956 if (!inSecureState(tc
) && ArmSystem::haveEL(tc
, EL2
))
957 lower_32
= ELIs32(tc
, EL2
);
959 lower_32
= ELIs32(tc
, EL1
);
961 lower_32
= ELIs32(tc
, static_cast<ExceptionLevel
>(toEL
- 1));
965 return vals
.lowerEL32Offset
;
966 return vals
.lowerEL64Offset
;
971 // SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx)
974 // esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32;
975 // esr.il = !machInst.thumb;
976 // if (machInst.aarch64)
977 // esr.imm16 = bits(machInst.instBits, 20, 5);
978 // else if (machInst.thumb)
979 // esr.imm16 = bits(machInst.instBits, 7, 0);
981 // esr.imm16 = bits(machInst.instBits, 15, 0);
982 // tc->setMiscReg(esr_idx, esr);
986 SecureMonitorCall::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
989 ArmFault::invoke(tc
, inst
);
995 SecureMonitorCall::ec(ThreadContext
*tc
) const
997 return (from64
? EC_SMC_64
: vals
.ec
);
1001 SupervisorTrap::routeToHyp(ThreadContext
*tc
) const
1005 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1006 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR_EL2
);
1007 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
1009 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
1010 toHyp
|= !inSecureState(scr
, cpsr
) && hcr
.tge
&& (currEL(tc
) == EL0
);
1015 SupervisorTrap::iss() const
1017 // If SupervisorTrap is routed to hypervisor, iss field is 0.
1025 SupervisorTrap::ec(ThreadContext
*tc
) const
1030 return (overrideEc
!= EC_INVALID
) ? overrideEc
: vals
.ec
;
1034 SecureMonitorTrap::ec(ThreadContext
*tc
) const
1036 return (overrideEc
!= EC_INVALID
) ? overrideEc
:
1037 (from64
? EC_SMC_64
: vals
.ec
);
1042 AbortFault
<T
>::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
1044 if (tranMethod
== ArmFault::UnknownTran
) {
1045 tranMethod
= longDescFormatInUse(tc
) ? ArmFault::LpaeTran
1046 : ArmFault::VmsaTran
;
1048 if ((tranMethod
== ArmFault::VmsaTran
) && this->routeToMonitor(tc
)) {
1049 // See ARM ARM B3-1416
1050 bool override_LPAE
= false;
1051 TTBCR ttbcr_s
= tc
->readMiscReg(MISCREG_TTBCR_S
);
1052 TTBCR M5_VAR_USED ttbcr_ns
= tc
->readMiscReg(MISCREG_TTBCR_NS
);
1054 override_LPAE
= true;
1056 // Unimplemented code option, not seen in testing. May need
1057 // extension according to the manual exceprt above.
1058 DPRINTF(Faults
, "Warning: Incomplete translation method "
1059 "override detected.\n");
1062 tranMethod
= ArmFault::LpaeTran
;
1066 if (source
== ArmFault::AsynchronousExternalAbort
) {
1067 tc
->getCpuPtr()->clearInterrupt(tc
->threadId(), INT_ABT
, 0);
1069 // Get effective fault source encoding
1070 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
1072 // source must be determined BEFORE invoking generic routines which will
1073 // try to set hsr etc. and are based upon source!
1074 ArmFaultVals
<T
>::invoke(tc
, inst
);
1076 if (!this->to64
) { // AArch32
1077 FSR fsr
= getFsr(tc
);
1078 if (cpsr
.mode
== MODE_HYP
) {
1079 tc
->setMiscReg(T::HFarIndex
, faultAddr
);
1080 } else if (stage2
) {
1081 tc
->setMiscReg(MISCREG_HPFAR
, (faultAddr
>> 8) & ~0xf);
1082 tc
->setMiscReg(T::HFarIndex
, OVAddr
);
1084 tc
->setMiscReg(T::FsrIndex
, fsr
);
1085 tc
->setMiscReg(T::FarIndex
, faultAddr
);
1087 DPRINTF(Faults
, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\
1088 "tranMethod=%#x\n", source
, fsr
, faultAddr
, tranMethod
);
1090 // Set the FAR register. Nothing else to do if we are in AArch64 state
1091 // because the syndrome register has already been set inside invoke64()
1093 // stage 2 fault, set HPFAR_EL2 to the faulting IPA
1094 // and FAR_EL2 to the Original VA
1095 tc
->setMiscReg(AbortFault
<T
>::getFaultAddrReg64(), OVAddr
);
1096 tc
->setMiscReg(MISCREG_HPFAR_EL2
, bits(faultAddr
, 47, 12) << 4);
1098 DPRINTF(Faults
, "Abort Fault (Stage 2) VA: 0x%x IPA: 0x%x\n",
1101 tc
->setMiscReg(AbortFault
<T
>::getFaultAddrReg64(), faultAddr
);
1108 AbortFault
<T
>::setSyndrome(ThreadContext
*tc
, MiscRegIndex syndrome_reg
)
1110 srcEncoded
= getFaultStatusCode(tc
);
1111 if (srcEncoded
== ArmFault::FaultSourceInvalid
) {
1112 panic("Invalid fault source\n");
1114 ArmFault::setSyndrome(tc
, syndrome_reg
);
1119 AbortFault
<T
>::getFaultStatusCode(ThreadContext
*tc
) const
1122 panic_if(!this->faultUpdated
,
1123 "Trying to use un-updated ArmFault internal variables\n");
1129 assert(tranMethod
!= ArmFault::UnknownTran
);
1130 if (tranMethod
== ArmFault::LpaeTran
) {
1131 fsc
= ArmFault::longDescFaultSources
[source
];
1133 fsc
= ArmFault::shortDescFaultSources
[source
];
1137 fsc
= ArmFault::aarch64FaultSources
[source
];
1145 AbortFault
<T
>::getFsr(ThreadContext
*tc
) const
1149 auto fsc
= getFaultStatusCode(tc
);
1152 assert(tranMethod
!= ArmFault::UnknownTran
);
1153 if (tranMethod
== ArmFault::LpaeTran
) {
1157 fsr
.fsLow
= bits(fsc
, 3, 0);
1158 fsr
.fsHigh
= bits(fsc
, 4);
1159 fsr
.domain
= static_cast<uint8_t>(domain
);
1162 fsr
.wnr
= (write
? 1 : 0);
1170 AbortFault
<T
>::abortDisable(ThreadContext
*tc
)
1172 if (ArmSystem::haveSecurity(tc
)) {
1173 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1174 return (!scr
.ns
|| scr
.aw
);
1181 AbortFault
<T
>::annotate(ArmFault::AnnotationIDs id
, uint64_t val
)
1185 case ArmFault::S1PTW
:
1192 // Just ignore unknown ID's
1200 AbortFault
<T
>::iss() const
1204 val
= srcEncoded
& 0x3F;
1212 AbortFault
<T
>::isMMUFault() const
1214 // NOTE: Not relying on LL information being aligned to lowest bits here
1216 (source
== ArmFault::AlignmentFault
) ||
1217 ((source
>= ArmFault::TranslationLL
) &&
1218 (source
< ArmFault::TranslationLL
+ 4)) ||
1219 ((source
>= ArmFault::AccessFlagLL
) &&
1220 (source
< ArmFault::AccessFlagLL
+ 4)) ||
1221 ((source
>= ArmFault::DomainLL
) &&
1222 (source
< ArmFault::DomainLL
+ 4)) ||
1223 ((source
>= ArmFault::PermissionLL
) &&
1224 (source
< ArmFault::PermissionLL
+ 4));
1229 AbortFault
<T
>::getFaultVAddr(Addr
&va
) const
1231 va
= (stage2
? OVAddr
: faultAddr
);
1236 PrefetchAbort::ec(ThreadContext
*tc
) const
1241 return EC_PREFETCH_ABORT_CURR_EL
;
1243 return EC_PREFETCH_ABORT_LOWER_EL
;
1246 // Abort faults have different EC codes depending on whether
1247 // the fault originated within HYP mode, or not. So override
1248 // the method and add the extra adjustment of the EC value.
1250 ExceptionClass ec
= ArmFaultVals
<PrefetchAbort
>::vals
.ec
;
1252 CPSR spsr
= tc
->readMiscReg(MISCREG_SPSR_HYP
);
1253 if (spsr
.mode
== MODE_HYP
) {
1254 ec
= ((ExceptionClass
) (((uint32_t) ec
) + 1));
1261 PrefetchAbort::routeToMonitor(ThreadContext
*tc
) const
1265 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1267 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1269 return scr
.ea
&& !isMMUFault();
1273 PrefetchAbort::routeToHyp(ThreadContext
*tc
) const
1277 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1278 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
1279 HDCR hdcr
= tc
->readMiscRegNoEffect(MISCREG_HDCR
);
1281 // if in Hyp mode then stay in Hyp mode
1282 toHyp
= scr
.ns
&& (currEL(tc
) == EL2
);
1283 // otherwise, check whether to take to Hyp mode through Hyp Trap vector
1285 ((source
== DebugEvent
) && hdcr
.tde
&& (currEL(tc
) != EL2
)) ||
1286 ((source
== SynchronousExternalAbort
) && hcr
.tge
&&
1287 (currEL(tc
) == EL0
))) && !inSecureState(tc
);
1292 DataAbort::ec(ThreadContext
*tc
) const
1296 if (source
== ArmFault::AsynchronousExternalAbort
) {
1297 panic("Asynchronous External Abort should be handled with "
1298 "SystemErrors (SErrors)!");
1301 return EC_DATA_ABORT_CURR_EL
;
1303 return EC_DATA_ABORT_LOWER_EL
;
1306 // Abort faults have different EC codes depending on whether
1307 // the fault originated within HYP mode, or not. So override
1308 // the method and add the extra adjustment of the EC value.
1310 ExceptionClass ec
= ArmFaultVals
<DataAbort
>::vals
.ec
;
1312 CPSR spsr
= tc
->readMiscReg(MISCREG_SPSR_HYP
);
1313 if (spsr
.mode
== MODE_HYP
) {
1314 ec
= ((ExceptionClass
) (((uint32_t) ec
) + 1));
1321 DataAbort::routeToMonitor(ThreadContext
*tc
) const
1325 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1327 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1329 return scr
.ea
&& !isMMUFault();
1333 DataAbort::routeToHyp(ThreadContext
*tc
) const
1337 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1338 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
1339 HDCR hdcr
= tc
->readMiscRegNoEffect(MISCREG_HDCR
);
1341 // if in Hyp mode then stay in Hyp mode
1342 toHyp
= scr
.ns
&& (currEL(tc
) == EL2
);
1343 // otherwise, check whether to take to Hyp mode through Hyp Trap vector
1345 ((currEL(tc
) != EL2
) &&
1346 (((source
== AsynchronousExternalAbort
) && hcr
.amo
) ||
1347 ((source
== DebugEvent
) && hdcr
.tde
))) ||
1348 ((currEL(tc
) == EL0
) && hcr
.tge
&&
1349 ((source
== AlignmentFault
) ||
1350 (source
== SynchronousExternalAbort
)))) && !inSecureState(tc
);
1355 DataAbort::iss() const
1359 // Add on the data abort specific fields to the generic abort ISS value
1360 val
= AbortFault
<DataAbort
>::iss();
1364 // ISS is valid if not caused by a stage 1 page table walk, and when taken
1365 // to AArch64 only when directed to EL2
1366 if (!s1ptw
&& stage2
&& (!to64
|| toEL
== EL2
)) {
1372 // AArch64 only. These assignments are safe on AArch32 as well
1373 // because these vars are initialized to false
1382 DataAbort::annotate(AnnotationIDs id
, uint64_t val
)
1384 AbortFault
<DataAbort
>::annotate(id
, val
);
1413 // Just ignore unknown ID's
1420 VirtualDataAbort::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
1422 AbortFault
<VirtualDataAbort
>::invoke(tc
, inst
);
1423 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
1425 tc
->setMiscRegNoEffect(MISCREG_HCR
, hcr
);
1429 Interrupt::routeToMonitor(ThreadContext
*tc
) const
1431 assert(ArmSystem::haveSecurity(tc
));
1434 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1436 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1441 Interrupt::routeToHyp(ThreadContext
*tc
) const
1445 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1446 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
1447 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
1448 // Determine whether IRQs are routed to Hyp mode.
1449 toHyp
= (!scr
.irq
&& hcr
.imo
&& !inSecureState(tc
)) ||
1450 (cpsr
.mode
== MODE_HYP
);
1455 Interrupt::abortDisable(ThreadContext
*tc
)
1457 if (ArmSystem::haveSecurity(tc
)) {
1458 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1459 return (!scr
.ns
|| scr
.aw
);
1464 VirtualInterrupt::VirtualInterrupt()
1468 FastInterrupt::routeToMonitor(ThreadContext
*tc
) const
1470 assert(ArmSystem::haveSecurity(tc
));
1473 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1475 scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1480 FastInterrupt::routeToHyp(ThreadContext
*tc
) const
1484 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1485 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
1486 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
1487 // Determine whether IRQs are routed to Hyp mode.
1488 toHyp
= (!scr
.fiq
&& hcr
.fmo
&& !inSecureState(tc
)) ||
1489 (cpsr
.mode
== MODE_HYP
);
1494 FastInterrupt::abortDisable(ThreadContext
*tc
)
1496 if (ArmSystem::haveSecurity(tc
)) {
1497 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1498 return (!scr
.ns
|| scr
.aw
);
1504 FastInterrupt::fiqDisable(ThreadContext
*tc
)
1506 if (ArmSystem::haveVirtualization(tc
)) {
1508 } else if (ArmSystem::haveSecurity(tc
)) {
1509 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR
);
1510 return (!scr
.ns
|| scr
.fw
);
1515 VirtualFastInterrupt::VirtualFastInterrupt()
1519 PCAlignmentFault::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
1521 ArmFaultVals
<PCAlignmentFault
>::invoke(tc
, inst
);
1524 tc
->setMiscReg(getFaultAddrReg64(), faultPC
);
1528 PCAlignmentFault::routeToHyp(ThreadContext
*tc
) const
1532 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1533 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR_EL2
);
1534 CPSR cpsr
= tc
->readMiscRegNoEffect(MISCREG_CPSR
);
1536 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
1537 toHyp
|= !inSecureState(scr
, cpsr
) && hcr
.tge
&& (currEL(tc
) == EL0
);
1541 SPAlignmentFault::SPAlignmentFault()
1544 SystemError::SystemError()
1548 SystemError::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
)
1550 tc
->getCpuPtr()->clearInterrupt(tc
->threadId(), INT_ABT
, 0);
1551 ArmFault::invoke(tc
, inst
);
1555 SystemError::routeToMonitor(ThreadContext
*tc
) const
1557 assert(ArmSystem::haveSecurity(tc
));
1559 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1564 SystemError::routeToHyp(ThreadContext
*tc
) const
1569 SCR scr
= tc
->readMiscRegNoEffect(MISCREG_SCR_EL3
);
1570 HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR
);
1572 toHyp
= (!scr
.ea
&& hcr
.amo
&& !inSecureState(tc
)) ||
1573 (!scr
.ea
&& !scr
.rw
&& !hcr
.amo
&& !inSecureState(tc
));
1578 SoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst _mach_inst
, uint32_t _iss
)
1579 : ArmFaultVals
<SoftwareBreakpoint
>(_mach_inst
, _iss
)
1583 SoftwareBreakpoint::routeToHyp(ThreadContext
*tc
) const
1585 const bool have_el2
= ArmSystem::haveVirtualization(tc
);
1587 const HCR hcr
= tc
->readMiscRegNoEffect(MISCREG_HCR_EL2
);
1588 const HDCR mdcr
= tc
->readMiscRegNoEffect(MISCREG_MDCR_EL2
);
1590 return have_el2
&& !inSecureState(tc
) && fromEL
<= EL1
&&
1591 (hcr
.tge
|| mdcr
.tde
);
1595 SoftwareBreakpoint::ec(ThreadContext
*tc
) const
1597 return from64
? EC_SOFTWARE_BREAKPOINT_64
: vals
.ec
;
1601 ArmSev::invoke(ThreadContext
*tc
, const StaticInstPtr
&inst
) {
1602 DPRINTF(Faults
, "Invoking ArmSev Fault\n");
1606 // Set sev_mailbox to 1, clear the pending interrupt from remote
1607 // SEV execution and let pipeline continue as pcState is still
1609 tc
->setMiscReg(MISCREG_SEV_MAILBOX
, 1);
1610 tc
->getCpuPtr()->clearInterrupt(tc
->threadId(), INT_SEV
, 0);
1613 // Instantiate all the templates to make the linker happy
1614 template class ArmFaultVals
<Reset
>;
1615 template class ArmFaultVals
<UndefinedInstruction
>;
1616 template class ArmFaultVals
<SupervisorCall
>;
1617 template class ArmFaultVals
<SecureMonitorCall
>;
1618 template class ArmFaultVals
<HypervisorCall
>;
1619 template class ArmFaultVals
<PrefetchAbort
>;
1620 template class ArmFaultVals
<DataAbort
>;
1621 template class ArmFaultVals
<VirtualDataAbort
>;
1622 template class ArmFaultVals
<HypervisorTrap
>;
1623 template class ArmFaultVals
<Interrupt
>;
1624 template class ArmFaultVals
<VirtualInterrupt
>;
1625 template class ArmFaultVals
<FastInterrupt
>;
1626 template class ArmFaultVals
<VirtualFastInterrupt
>;
1627 template class ArmFaultVals
<SupervisorTrap
>;
1628 template class ArmFaultVals
<SecureMonitorTrap
>;
1629 template class ArmFaultVals
<PCAlignmentFault
>;
1630 template class ArmFaultVals
<SPAlignmentFault
>;
1631 template class ArmFaultVals
<SystemError
>;
1632 template class ArmFaultVals
<SoftwareBreakpoint
>;
1633 template class ArmFaultVals
<ArmSev
>;
1634 template class AbortFault
<PrefetchAbort
>;
1635 template class AbortFault
<DataAbort
>;
1636 template class AbortFault
<VirtualDataAbort
>;
1639 IllegalInstSetStateFault::IllegalInstSetStateFault()
1643 getFaultVAddr(Fault fault
, Addr
&va
)
1645 auto arm_fault
= dynamic_cast<ArmFault
*>(fault
.get());
1648 return arm_fault
->getFaultVAddr(va
);
1650 auto pgt_fault
= dynamic_cast<GenericPageTableFault
*>(fault
.get());
1652 va
= pgt_fault
->getFaultVAddr();
1656 auto align_fault
= dynamic_cast<GenericAlignmentFault
*>(fault
.get());
1658 va
= align_fault
->getFaultVAddr();
1662 // Return false since it's not an address triggered exception
1667 } // namespace ArmISA