9e32a23a391cc2f0f493e8c27e2b8177d8010372
2 * Copyright (c) 2010 ARM Limited
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14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
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45 #include "arch/arm/faults.hh"
46 #include "cpu/thread_context.hh"
47 #include "cpu/base.hh"
48 #include "base/trace.hh"
53 template<> ArmFaultBase::FaultVals ArmFault
<Reset
>::vals
=
54 {"reset", 0x00, MODE_SVC
, 0, 0, true, true};
56 template<> ArmFaultBase::FaultVals ArmFault
<UndefinedInstruction
>::vals
=
57 {"Undefined Instruction", 0x04, MODE_UNDEFINED
, 4 ,2, false, false} ;
59 template<> ArmFaultBase::FaultVals ArmFault
<SupervisorCall
>::vals
=
60 {"Supervisor Call", 0x08, MODE_SVC
, 4, 2, false, false};
62 template<> ArmFaultBase::FaultVals ArmFault
<PrefetchAbort
>::vals
=
63 {"Prefetch Abort", 0x0C, MODE_ABORT
, 4, 4, true, false};
65 template<> ArmFaultBase::FaultVals ArmFault
<DataAbort
>::vals
=
66 {"Data Abort", 0x10, MODE_ABORT
, 8, 8, true, false};
68 template<> ArmFaultBase::FaultVals ArmFault
<Interrupt
>::vals
=
69 {"IRQ", 0x18, MODE_IRQ
, 4, 4, true, false};
71 template<> ArmFaultBase::FaultVals ArmFault
<FastInterrupt
>::vals
=
72 {"FIQ", 0x1C, MODE_FIQ
, 4, 4, true, true};
75 ArmFaultBase::getVector(ThreadContext
*tc
)
79 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR
);
81 // panic if SCTLR.VE because I have no idea what to do with vectored
87 return offset() + HighVecs
;
94 ArmFaultBase::invoke(ThreadContext
*tc
)
97 FaultBase::invoke(tc
);
100 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR
);
101 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
102 CPSR saved_cpsr
= tc
->readMiscReg(MISCREG_CPSR
) |
103 tc
->readIntReg(INTREG_CONDCODES
);
106 cpsr
.mode
= nextMode();
107 cpsr
.it1
= cpsr
.it2
= 0;
111 cpsr
.a
= cpsr
.a
| abortDisable();
112 cpsr
.f
= cpsr
.f
| fiqDisable();
114 tc
->setMiscReg(MISCREG_CPSR
, cpsr
);
115 tc
->setIntReg(INTREG_LR
, tc
->readPC() +
116 (saved_cpsr
.t
? thumbPcOffset() : armPcOffset()));
118 switch (nextMode()) {
120 tc
->setMiscReg(MISCREG_SPSR_FIQ
, saved_cpsr
);
123 tc
->setMiscReg(MISCREG_SPSR_IRQ
, saved_cpsr
);
126 tc
->setMiscReg(MISCREG_SPSR_SVC
, saved_cpsr
);
129 tc
->setMiscReg(MISCREG_SPSR_UND
, saved_cpsr
);
132 tc
->setMiscReg(MISCREG_SPSR_ABT
, saved_cpsr
);
135 panic("unknown Mode\n");
138 Addr pc
= tc
->readPC();
139 DPRINTF(Faults
, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n",
140 name(), cpsr
, pc
, tc
->readIntReg(INTREG_LR
));
141 Addr newPc
= getVector(tc
) | (sctlr
.te
? (ULL(1) << PcTBitShift
) : 0);
143 tc
->setNextPC(newPc
+ cpsr
.t
? 2 : 4 );
149 UndefinedInstruction::invoke(ThreadContext
*tc
)
151 assert(unknown
|| mnemonic
!= NULL
);
153 panic("Attempted to execute unknown instruction "
154 "(inst 0x%08x, opcode 0x%x, binary:%s)",
155 machInst
, machInst
.opcode
, inst2string(machInst
));
157 panic("Attempted to execute unimplemented instruction '%s' "
158 "(inst 0x%08x, opcode 0x%x, binary:%s)",
159 mnemonic
, machInst
, machInst
.opcode
, inst2string(machInst
));
163 #endif // FULL_SYSTEM
165 // return via SUBS pc, lr, xxx; rfe, movs, ldm
169 } // namespace ArmISA