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45 #include "arch/arm/faults.hh"
46 #include "cpu/thread_context.hh"
47 #include "cpu/base.hh"
48 #include "base/trace.hh"
53 template<> ArmFault::FaultVals ArmFaultVals
<Reset
>::vals
=
54 {"reset", 0x00, MODE_SVC
, 0, 0, true, true};
56 template<> ArmFault::FaultVals ArmFaultVals
<UndefinedInstruction
>::vals
=
57 {"Undefined Instruction", 0x04, MODE_UNDEFINED
, 4 ,2, false, false} ;
59 template<> ArmFault::FaultVals ArmFaultVals
<SupervisorCall
>::vals
=
60 {"Supervisor Call", 0x08, MODE_SVC
, 4, 2, false, false};
62 template<> ArmFault::FaultVals ArmFaultVals
<PrefetchAbort
>::vals
=
63 {"Prefetch Abort", 0x0C, MODE_ABORT
, 4, 4, true, false};
65 template<> ArmFault::FaultVals ArmFaultVals
<DataAbort
>::vals
=
66 {"Data Abort", 0x10, MODE_ABORT
, 8, 8, true, false};
68 template<> ArmFault::FaultVals ArmFaultVals
<Interrupt
>::vals
=
69 {"IRQ", 0x18, MODE_IRQ
, 4, 4, true, false};
71 template<> ArmFault::FaultVals ArmFaultVals
<FastInterrupt
>::vals
=
72 {"FIQ", 0x1C, MODE_FIQ
, 4, 4, true, true};
75 ArmFault::getVector(ThreadContext
*tc
)
79 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR
);
81 // panic if SCTLR.VE because I have no idea what to do with vectored
87 return offset() + HighVecs
;
94 ArmFault::invoke(ThreadContext
*tc
)
97 FaultBase::invoke(tc
);
100 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR
);
101 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
102 CPSR saved_cpsr
= tc
->readMiscReg(MISCREG_CPSR
) |
103 tc
->readIntReg(INTREG_CONDCODES
);
106 cpsr
.mode
= nextMode();
107 cpsr
.it1
= cpsr
.it2
= 0;
111 cpsr
.a
= cpsr
.a
| abortDisable();
112 cpsr
.f
= cpsr
.f
| fiqDisable();
115 tc
->setMiscReg(MISCREG_CPSR
, cpsr
);
116 tc
->setIntReg(INTREG_LR
, tc
->readPC() +
117 (saved_cpsr
.t
? thumbPcOffset() : armPcOffset()));
119 switch (nextMode()) {
121 tc
->setMiscReg(MISCREG_SPSR_FIQ
, saved_cpsr
);
124 tc
->setMiscReg(MISCREG_SPSR_IRQ
, saved_cpsr
);
127 tc
->setMiscReg(MISCREG_SPSR_SVC
, saved_cpsr
);
130 tc
->setMiscReg(MISCREG_SPSR_UND
, saved_cpsr
);
133 tc
->setMiscReg(MISCREG_SPSR_ABT
, saved_cpsr
);
136 panic("unknown Mode\n");
139 Addr pc
= tc
->readPC();
140 DPRINTF(Faults
, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n",
141 name(), cpsr
, pc
, tc
->readIntReg(INTREG_LR
));
142 Addr newPc
= getVector(tc
) | (sctlr
.te
? (ULL(1) << PcTBitShift
) : 0);
144 tc
->setNextPC(newPc
+ cpsr
.t
? 2 : 4 );
151 UndefinedInstruction::invoke(ThreadContext
*tc
)
153 assert(unknown
|| mnemonic
!= NULL
);
155 panic("Attempted to execute unknown instruction "
156 "(inst 0x%08x, opcode 0x%x, binary:%s)",
157 machInst
, machInst
.opcode
, inst2string(machInst
));
159 panic("Attempted to execute unimplemented instruction '%s' "
160 "(inst 0x%08x, opcode 0x%x, binary:%s)",
161 mnemonic
, machInst
, machInst
.opcode
, inst2string(machInst
));
166 SupervisorCall::invoke(ThreadContext
*tc
)
168 // As of now, there isn't a 32 bit thumb version of this instruction.
169 assert(!machInst
.bigThumb
);
171 if (machInst
.thumb
) {
172 callNum
= bits(machInst
, 7, 0);
174 callNum
= bits(machInst
, 23, 0);
177 callNum
= tc
->readIntReg(INTREG_R7
);
179 tc
->syscall(callNum
);
181 // Advance the PC since that won't happen automatically.
182 tc
->setPC(tc
->readNextPC());
183 tc
->setNextPC(tc
->readNextNPC());
186 #endif // FULL_SYSTEM
190 AbortFault
<T
>::invoke(ThreadContext
*tc
)
192 ArmFaultVals
<T
>::invoke(tc
);
194 fsr
.fsLow
= bits(status
, 3, 0);
195 fsr
.fsHigh
= bits(status
, 4);
197 fsr
.wnr
= (write
? 1 : 0);
199 tc
->setMiscReg(T::FsrIndex
, fsr
);
200 tc
->setMiscReg(T::FarIndex
, faultAddr
);
203 template void AbortFault
<PrefetchAbort
>::invoke(ThreadContext
*tc
);
204 template void AbortFault
<DataAbort
>::invoke(ThreadContext
*tc
);
206 // return via SUBS pc, lr, xxx; rfe, movs, ldm
210 } // namespace ArmISA