src/arch/arm/faults.cc

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2007-2008 The Florida State University
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Ali Saidi
  42  *          Gabe Black
  43  */
  44
  45 #include "arch/arm/faults.hh"
  46 #include "base/trace.hh"
  47 #include "cpu/base.hh"
  48 #include "cpu/thread_context.hh"
  49 #include "debug/Faults.hh"
  50
  51 namespace ArmISA
  52 {
  53
  54 template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals =
  55     {"reset", 0x00, MODE_SVC, 0, 0, true, true};
  56
  57 template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals =
  58     {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ;
  59
  60 template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals =
  61     {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false};
  62
  63 template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals =
  64     {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false};
  65
  66 template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals =
  67     {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false};
  68
  69 template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals =
  70     {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
  71
  72 template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals =
  73     {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
  74
  75 template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals =
  76     {"Pipe Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
  77
  78 template<> ArmFault::FaultVals ArmFaultVals<ReExec>::vals =
  79     {"ReExec Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
  80
  81 Addr
  82 ArmFault::getVector(ThreadContext *tc)
  83 {
  84     // ARM ARM B1-3
  85
  86     SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
  87
  88     // panic if SCTLR.VE because I have no idea what to do with vectored
  89     // interrupts
  90     assert(!sctlr.ve);
  91
  92     if (!sctlr.v)
  93         return offset();
  94     return offset() + HighVecs;
  95
  96 }
  97
  98 #if FULL_SYSTEM
  99
 100 void
 101 ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 102 {
 103     // ARM ARM B1.6.3
 104     FaultBase::invoke(tc);
 105     countStat()++;
 106
 107     SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
 108     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 109     CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
 110                       tc->readIntReg(INTREG_CONDCODES_F) |
 111                       tc->readIntReg(INTREG_CONDCODES_Q) |
 112                       tc->readIntReg(INTREG_CONDCODES_GE);
 113     Addr curPc M5_VAR_USED = tc->pcState().pc();
 114     ITSTATE it = tc->pcState().itstate();
 115     saved_cpsr.it2 = it.top6;
 116     saved_cpsr.it1 = it.bottom2;
 117
 118     cpsr.mode = nextMode();
 119     cpsr.it1 = cpsr.it2 = 0;
 120     cpsr.j = 0;
 121
 122     cpsr.t = sctlr.te;
 123     cpsr.a = cpsr.a | abortDisable();
 124     cpsr.f = cpsr.f | fiqDisable();
 125     cpsr.i = 1;
 126     cpsr.e = sctlr.ee;
 127     tc->setMiscReg(MISCREG_CPSR, cpsr);
 128     tc->setIntReg(INTREG_LR, curPc +
 129             (saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
 130
 131     switch (nextMode()) {
 132       case MODE_FIQ:
 133         tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
 134         break;
 135       case MODE_IRQ:
 136         tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
 137         break;
 138       case MODE_SVC:
 139         tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
 140         break;
 141       case MODE_UNDEFINED:
 142         tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
 143         break;
 144       case MODE_ABORT:
 145         tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
 146         break;
 147       default:
 148         panic("unknown Mode\n");
 149     }
 150
 151     Addr newPc = getVector(tc);
 152     DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
 153             name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
 154     PCState pc(newPc);
 155     pc.thumb(cpsr.t);
 156     pc.nextThumb(pc.thumb());
 157     pc.jazelle(cpsr.j);
 158     pc.nextJazelle(pc.jazelle());
 159     tc->pcState(pc);
 160 }
 161
 162 void
 163 Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
 164 {
 165     tc->getCpuPtr()->clearInterrupts();
 166     tc->clearArchRegs();
 167     ArmFault::invoke(tc, inst);
 168 }
 169
 170 #else
 171
 172 void
 173 UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
 174 {
 175     // If the mnemonic isn't defined this has to be an unknown instruction.
 176     assert(unknown || mnemonic != NULL);
 177     if (disabled) {
 178         panic("Attempted to execute disabled instruction "
 179                 "'%s' (inst 0x%08x)", mnemonic, machInst);
 180     } else if (unknown) {
 181         panic("Attempted to execute unknown instruction (inst 0x%08x)",
 182               machInst);
 183     } else {
 184         panic("Attempted to execute unimplemented instruction "
 185                 "'%s' (inst 0x%08x)", mnemonic, machInst);
 186     }
 187 }
 188
 189 void
 190 SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
 191 {
 192     // As of now, there isn't a 32 bit thumb version of this instruction.
 193     assert(!machInst.bigThumb);
 194     uint32_t callNum;
 195     callNum = tc->readIntReg(INTREG_R7);
 196     tc->syscall(callNum);
 197
 198     // Advance the PC since that won't happen automatically.
 199     PCState pc = tc->pcState();
 200     assert(inst);
 201     inst->advancePC(pc);
 202     tc->pcState(pc);
 203 }
 204
 205 #endif // FULL_SYSTEM
 206
 207 template<class T>
 208 void
 209 AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
 210 {
 211     ArmFaultVals<T>::invoke(tc, inst);
 212     FSR fsr = 0;
 213     fsr.fsLow = bits(status, 3, 0);
 214     fsr.fsHigh = bits(status, 4);
 215     fsr.domain = domain;
 216     fsr.wnr = (write ? 1 : 0);
 217     fsr.ext = 0;
 218     tc->setMiscReg(T::FsrIndex, fsr);
 219     tc->setMiscReg(T::FarIndex, faultAddr);
 220 }
 221
 222 void
 223 FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
 224     DPRINTF(Faults, "Invoking FlushPipe Fault\n");
 225
 226     // Set the PC to the next instruction of the faulting instruction.
 227     // Net effect is simply squashing all instructions behind and
 228     // start refetching from the next instruction.
 229     PCState pc = tc->pcState();
 230     assert(inst);
 231     inst->advancePC(pc);
 232     tc->pcState(pc);
 233 }
 234
 235 void
 236 ReExec::invoke(ThreadContext *tc, StaticInstPtr inst) {
 237     DPRINTF(Faults, "Invoking ReExec Fault\n");
 238
 239     // Set the PC to then the faulting instruction.
 240     // Net effect is simply squashing all instructions including this
 241     // instruction and refetching/rexecuting current instruction
 242     PCState pc = tc->pcState();
 243     tc->pcState(pc);
 244 }
 245
 246 template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc,
 247                                                 StaticInstPtr inst);
 248 template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
 249                                             StaticInstPtr inst);
 250
 251 // return via SUBS pc, lr, xxx; rfe, movs, ldm
 252
 253 } // namespace ArmISA