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arm: enable EL2 support
[gem5.git] / src / arch / arm / faults.cc
1 /*
2 * Copyright (c) 2010, 2012-2014, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 * Gabe Black
43 * Giacomo Gabrielli
44 * Thomas Grocutt
45 */
46
47 #include "arch/arm/faults.hh"
48 #include "arch/arm/system.hh"
49 #include "arch/arm/utility.hh"
50 #include "arch/arm/insts/static_inst.hh"
51 #include "base/compiler.hh"
52 #include "base/trace.hh"
53 #include "cpu/base.hh"
54 #include "cpu/thread_context.hh"
55 #include "debug/Faults.hh"
56 #include "sim/full_system.hh"
57
58 namespace ArmISA
59 {
60
61 uint8_t ArmFault::shortDescFaultSources[] = {
62 0x01, // AlignmentFault
63 0x04, // InstructionCacheMaintenance
64 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID)
65 0x0c, // SynchExtAbtOnTranslTableWalkL1
66 0x0e, // SynchExtAbtOnTranslTableWalkL2
67 0xff, // SynchExtAbtOnTranslTableWalkL3 (INVALID)
68 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID)
69 0x1c, // SynchPtyErrOnTranslTableWalkL1
70 0x1e, // SynchPtyErrOnTranslTableWalkL2
71 0xff, // SynchPtyErrOnTranslTableWalkL3 (INVALID)
72 0xff, // TranslationL0 (INVALID)
73 0x05, // TranslationL1
74 0x07, // TranslationL2
75 0xff, // TranslationL3 (INVALID)
76 0xff, // AccessFlagL0 (INVALID)
77 0x03, // AccessFlagL1
78 0x06, // AccessFlagL2
79 0xff, // AccessFlagL3 (INVALID)
80 0xff, // DomainL0 (INVALID)
81 0x09, // DomainL1
82 0x0b, // DomainL2
83 0xff, // DomainL3 (INVALID)
84 0xff, // PermissionL0 (INVALID)
85 0x0d, // PermissionL1
86 0x0f, // PermissionL2
87 0xff, // PermissionL3 (INVALID)
88 0x02, // DebugEvent
89 0x08, // SynchronousExternalAbort
90 0x10, // TLBConflictAbort
91 0x19, // SynchPtyErrOnMemoryAccess
92 0x16, // AsynchronousExternalAbort
93 0x18, // AsynchPtyErrOnMemoryAccess
94 0xff, // AddressSizeL0 (INVALID)
95 0xff, // AddressSizeL1 (INVALID)
96 0xff, // AddressSizeL2 (INVALID)
97 0xff, // AddressSizeL3 (INVALID)
98 0x40, // PrefetchTLBMiss
99 0x80 // PrefetchUncacheable
100 };
101
102 static_assert(sizeof(ArmFault::shortDescFaultSources) ==
103 ArmFault::NumFaultSources,
104 "Invalid size of ArmFault::shortDescFaultSources[]");
105
106 uint8_t ArmFault::longDescFaultSources[] = {
107 0x21, // AlignmentFault
108 0xff, // InstructionCacheMaintenance (INVALID)
109 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID)
110 0x15, // SynchExtAbtOnTranslTableWalkL1
111 0x16, // SynchExtAbtOnTranslTableWalkL2
112 0x17, // SynchExtAbtOnTranslTableWalkL3
113 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID)
114 0x1d, // SynchPtyErrOnTranslTableWalkL1
115 0x1e, // SynchPtyErrOnTranslTableWalkL2
116 0x1f, // SynchPtyErrOnTranslTableWalkL3
117 0xff, // TranslationL0 (INVALID)
118 0x05, // TranslationL1
119 0x06, // TranslationL2
120 0x07, // TranslationL3
121 0xff, // AccessFlagL0 (INVALID)
122 0x09, // AccessFlagL1
123 0x0a, // AccessFlagL2
124 0x0b, // AccessFlagL3
125 0xff, // DomainL0 (INVALID)
126 0x3d, // DomainL1
127 0x3e, // DomainL2
128 0xff, // DomainL3 (RESERVED)
129 0xff, // PermissionL0 (INVALID)
130 0x0d, // PermissionL1
131 0x0e, // PermissionL2
132 0x0f, // PermissionL3
133 0x22, // DebugEvent
134 0x10, // SynchronousExternalAbort
135 0x30, // TLBConflictAbort
136 0x18, // SynchPtyErrOnMemoryAccess
137 0x11, // AsynchronousExternalAbort
138 0x19, // AsynchPtyErrOnMemoryAccess
139 0xff, // AddressSizeL0 (INVALID)
140 0xff, // AddressSizeL1 (INVALID)
141 0xff, // AddressSizeL2 (INVALID)
142 0xff, // AddressSizeL3 (INVALID)
143 0x40, // PrefetchTLBMiss
144 0x80 // PrefetchUncacheable
145 };
146
147 static_assert(sizeof(ArmFault::longDescFaultSources) ==
148 ArmFault::NumFaultSources,
149 "Invalid size of ArmFault::longDescFaultSources[]");
150
151 uint8_t ArmFault::aarch64FaultSources[] = {
152 0x21, // AlignmentFault
153 0xff, // InstructionCacheMaintenance (INVALID)
154 0x14, // SynchExtAbtOnTranslTableWalkL0
155 0x15, // SynchExtAbtOnTranslTableWalkL1
156 0x16, // SynchExtAbtOnTranslTableWalkL2
157 0x17, // SynchExtAbtOnTranslTableWalkL3
158 0x1c, // SynchPtyErrOnTranslTableWalkL0
159 0x1d, // SynchPtyErrOnTranslTableWalkL1
160 0x1e, // SynchPtyErrOnTranslTableWalkL2
161 0x1f, // SynchPtyErrOnTranslTableWalkL3
162 0x04, // TranslationL0
163 0x05, // TranslationL1
164 0x06, // TranslationL2
165 0x07, // TranslationL3
166 0x08, // AccessFlagL0
167 0x09, // AccessFlagL1
168 0x0a, // AccessFlagL2
169 0x0b, // AccessFlagL3
170 // @todo: Section & Page Domain Fault in AArch64?
171 0xff, // DomainL0 (INVALID)
172 0xff, // DomainL1 (INVALID)
173 0xff, // DomainL2 (INVALID)
174 0xff, // DomainL3 (INVALID)
175 0x0c, // PermissionL0
176 0x0d, // PermissionL1
177 0x0e, // PermissionL2
178 0x0f, // PermissionL3
179 0xff, // DebugEvent (INVALID)
180 0x10, // SynchronousExternalAbort
181 0x30, // TLBConflictAbort
182 0x18, // SynchPtyErrOnMemoryAccess
183 0xff, // AsynchronousExternalAbort (INVALID)
184 0xff, // AsynchPtyErrOnMemoryAccess (INVALID)
185 0x00, // AddressSizeL0
186 0x01, // AddressSizeL1
187 0x02, // AddressSizeL2
188 0x03, // AddressSizeL3
189 0x40, // PrefetchTLBMiss
190 0x80 // PrefetchUncacheable
191 };
192
193 static_assert(sizeof(ArmFault::aarch64FaultSources) ==
194 ArmFault::NumFaultSources,
195 "Invalid size of ArmFault::aarch64FaultSources[]");
196
197 // Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode,
198 // {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap,
199 // {A, F} disable, class, stat
200 template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals = {
201 // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED
202 // location in AArch64)
203 "Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
204 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat()
205 };
206 template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals = {
207 "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED,
208 4, 2, 0, 0, true, false, false, EC_UNKNOWN, FaultStat()
209 };
210 template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals = {
211 "Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
212 4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP, FaultStat()
213 };
214 template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals = {
215 "Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON,
216 4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP, FaultStat()
217 };
218 template<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals = {
219 "Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
220 4, 4, 4, 4, true, false, false, EC_HVC, FaultStat()
221 };
222 template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals = {
223 "Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
224 4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP, FaultStat()
225 };
226 template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals = {
227 "Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
228 8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP, FaultStat()
229 };
230 template<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals = {
231 "Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
232 8, 8, 0, 0, true, true, false, EC_INVALID, FaultStat()
233 };
234 template<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals = {
235 // @todo: double check these values
236 "Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
237 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
238 };
239 template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals = {
240 "IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
241 4, 4, 0, 0, false, true, false, EC_UNKNOWN, FaultStat()
242 };
243 template<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals = {
244 "Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
245 4, 4, 0, 0, false, true, false, EC_INVALID, FaultStat()
246 };
247 template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals = {
248 "FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
249 4, 4, 0, 0, false, true, true, EC_UNKNOWN, FaultStat()
250 };
251 template<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals = {
252 "Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
253 4, 4, 0, 0, false, true, true, EC_INVALID, FaultStat()
254 };
255 template<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals = {
256 // Some dummy values (SupervisorTrap is AArch64-only)
257 "Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
258 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
259 };
260 template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals = {
261 // Some dummy values (SecureMonitorTrap is AArch64-only)
262 "Secure Monitor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_MON,
263 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
264 };
265 template<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals = {
266 // Some dummy values (PCAlignmentFault is AArch64-only)
267 "PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
268 0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT, FaultStat()
269 };
270 template<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals = {
271 // Some dummy values (SPAlignmentFault is AArch64-only)
272 "SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
273 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT, FaultStat()
274 };
275 template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals = {
276 // Some dummy values (SError is AArch64-only)
277 "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC,
278 0, 0, 0, 0, false, true, true, EC_SERROR, FaultStat()
279 };
280 template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals = {
281 // Some dummy values
282 "Pipe Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
283 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat()
284 };
285 template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals = {
286 // Some dummy values
287 "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
288 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat()
289 };
290 template<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals = {
291 // Some dummy values (SPAlignmentFault is AArch64-only)
292 "Illegal Inst Set State Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
293 0, 0, 0, 0, true, false, false, EC_ILLEGAL_INST, FaultStat()
294 };
295
296 Addr
297 ArmFault::getVector(ThreadContext *tc)
298 {
299 Addr base;
300
301 // ARM ARM issue C B1.8.1
302 bool haveSecurity = ArmSystem::haveSecurity(tc);
303
304 // panic if SCTLR.VE because I have no idea what to do with vectored
305 // interrupts
306 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
307 assert(!sctlr.ve);
308 // Check for invalid modes
309 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
310 assert(haveSecurity || cpsr.mode != MODE_MON);
311 assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
312
313 switch (cpsr.mode)
314 {
315 case MODE_MON:
316 base = tc->readMiscReg(MISCREG_MVBAR);
317 break;
318 case MODE_HYP:
319 base = tc->readMiscReg(MISCREG_HVBAR);
320 break;
321 default:
322 if (sctlr.v) {
323 base = HighVecs;
324 } else {
325 base = haveSecurity ? tc->readMiscReg(MISCREG_VBAR) : 0;
326 }
327 break;
328 }
329 return base + offset(tc);
330 }
331
332 Addr
333 ArmFault::getVector64(ThreadContext *tc)
334 {
335 Addr vbar;
336 switch (toEL) {
337 case EL3:
338 assert(ArmSystem::haveSecurity(tc));
339 vbar = tc->readMiscReg(MISCREG_VBAR_EL3);
340 break;
341 case EL2:
342 assert(ArmSystem::haveVirtualization(tc));
343 vbar = tc->readMiscReg(MISCREG_VBAR_EL2);
344 break;
345 case EL1:
346 vbar = tc->readMiscReg(MISCREG_VBAR_EL1);
347 break;
348 default:
349 panic("Invalid target exception level");
350 break;
351 }
352 return vbar + offset64();
353 }
354
355 MiscRegIndex
356 ArmFault::getSyndromeReg64() const
357 {
358 switch (toEL) {
359 case EL1:
360 return MISCREG_ESR_EL1;
361 case EL2:
362 return MISCREG_ESR_EL2;
363 case EL3:
364 return MISCREG_ESR_EL3;
365 default:
366 panic("Invalid exception level");
367 break;
368 }
369 }
370
371 MiscRegIndex
372 ArmFault::getFaultAddrReg64() const
373 {
374 switch (toEL) {
375 case EL1:
376 return MISCREG_FAR_EL1;
377 case EL2:
378 return MISCREG_FAR_EL2;
379 case EL3:
380 return MISCREG_FAR_EL3;
381 default:
382 panic("Invalid exception level");
383 break;
384 }
385 }
386
387 void
388 ArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
389 {
390 uint32_t value;
391 uint32_t exc_class = (uint32_t) ec(tc);
392 uint32_t issVal = iss();
393 assert(!from64 || ArmSystem::highestELIs64(tc));
394
395 value = exc_class << 26;
396
397 // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24,
398 // 0x25) for which the ISS information is not valid (ARMv7).
399 // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not
400 // valid it is treated as RES1.
401 if (to64) {
402 value |= 1 << 25;
403 } else if ((bits(exc_class, 5, 3) != 4) ||
404 (bits(exc_class, 2) && bits(issVal, 24))) {
405 if (!machInst.thumb || machInst.bigThumb)
406 value |= 1 << 25;
407 }
408 // Condition code valid for EC[5:4] nonzero
409 if (!from64 && ((bits(exc_class, 5, 4) == 0) &&
410 (bits(exc_class, 3, 0) != 0))) {
411 if (!machInst.thumb) {
412 uint32_t cond;
413 ConditionCode condCode = (ConditionCode) (uint32_t) machInst.condCode;
414 // If its on unconditional instruction report with a cond code of
415 // 0xE, ie the unconditional code
416 cond = (condCode == COND_UC) ? COND_AL : condCode;
417 value |= cond << 20;
418 value |= 1 << 24;
419 }
420 value |= bits(issVal, 19, 0);
421 } else {
422 value |= issVal;
423 }
424 tc->setMiscReg(syndrome_reg, value);
425 }
426
427 void
428 ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
429 {
430 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
431
432 if (ArmSystem::highestELIs64(tc)) { // ARMv8
433 // Determine source exception level and mode
434 fromMode = (OperatingMode) (uint8_t) cpsr.mode;
435 fromEL = opModeToEL(fromMode);
436 if (opModeIs64(fromMode))
437 from64 = true;
438
439 // Determine target exception level
440 if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc))
441 toEL = EL3;
442 else
443 toEL = opModeToEL(nextMode());
444 if (fromEL > toEL)
445 toEL = fromEL;
446
447 if (toEL == ArmSystem::highestEL(tc) || ELIs64(tc, toEL)) {
448 // Invoke exception handler in AArch64 state
449 to64 = true;
450 invoke64(tc, inst);
451 return;
452 }
453 }
454
455 // ARMv7 (ARM ARM issue C B1.9)
456
457 bool have_security = ArmSystem::haveSecurity(tc);
458 bool have_virtualization = ArmSystem::haveVirtualization(tc);
459
460 FaultBase::invoke(tc);
461 if (!FullSystem)
462 return;
463 countStat()++;
464
465 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
466 SCR scr = tc->readMiscReg(MISCREG_SCR);
467 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR);
468 saved_cpsr.nz = tc->readCCReg(CCREG_NZ);
469 saved_cpsr.c = tc->readCCReg(CCREG_C);
470 saved_cpsr.v = tc->readCCReg(CCREG_V);
471 saved_cpsr.ge = tc->readCCReg(CCREG_GE);
472
473 Addr curPc M5_VAR_USED = tc->pcState().pc();
474 ITSTATE it = tc->pcState().itstate();
475 saved_cpsr.it2 = it.top6;
476 saved_cpsr.it1 = it.bottom2;
477
478 // if we have a valid instruction then use it to annotate this fault with
479 // extra information. This is used to generate the correct fault syndrome
480 // information
481 if (inst) {
482 ArmStaticInst *armInst = reinterpret_cast<ArmStaticInst *>(inst.get());
483 armInst->annotateFault(this);
484 }
485
486 if (have_security && routeToMonitor(tc))
487 cpsr.mode = MODE_MON;
488 else if (have_virtualization && routeToHyp(tc))
489 cpsr.mode = MODE_HYP;
490 else
491 cpsr.mode = nextMode();
492
493 // Ensure Secure state if initially in Monitor mode
494 if (have_security && saved_cpsr.mode == MODE_MON) {
495 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
496 if (scr.ns) {
497 scr.ns = 0;
498 tc->setMiscRegNoEffect(MISCREG_SCR, scr);
499 }
500 }
501
502 // some bits are set differently if we have been routed to hyp mode
503 if (cpsr.mode == MODE_HYP) {
504 SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR);
505 cpsr.t = hsctlr.te;
506 cpsr.e = hsctlr.ee;
507 if (!scr.ea) {cpsr.a = 1;}
508 if (!scr.fiq) {cpsr.f = 1;}
509 if (!scr.irq) {cpsr.i = 1;}
510 } else if (cpsr.mode == MODE_MON) {
511 // Special case handling when entering monitor mode
512 cpsr.t = sctlr.te;
513 cpsr.e = sctlr.ee;
514 cpsr.a = 1;
515 cpsr.f = 1;
516 cpsr.i = 1;
517 } else {
518 cpsr.t = sctlr.te;
519 cpsr.e = sctlr.ee;
520
521 // The *Disable functions are virtual and different per fault
522 cpsr.a = cpsr.a | abortDisable(tc);
523 cpsr.f = cpsr.f | fiqDisable(tc);
524 cpsr.i = 1;
525 }
526 cpsr.it1 = cpsr.it2 = 0;
527 cpsr.j = 0;
528 tc->setMiscReg(MISCREG_CPSR, cpsr);
529
530 // Make sure mailbox sets to one always
531 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
532
533 // Clear the exclusive monitor
534 tc->setMiscReg(MISCREG_LOCKFLAG, 0);
535
536 if (cpsr.mode == MODE_HYP) {
537 tc->setMiscReg(MISCREG_ELR_HYP, curPc +
538 (saved_cpsr.t ? thumbPcOffset(true) : armPcOffset(true)));
539 } else {
540 tc->setIntReg(INTREG_LR, curPc +
541 (saved_cpsr.t ? thumbPcOffset(false) : armPcOffset(false)));
542 }
543
544 switch (cpsr.mode) {
545 case MODE_FIQ:
546 tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
547 break;
548 case MODE_IRQ:
549 tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
550 break;
551 case MODE_SVC:
552 tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
553 break;
554 case MODE_MON:
555 assert(have_security);
556 tc->setMiscReg(MISCREG_SPSR_MON, saved_cpsr);
557 break;
558 case MODE_ABORT:
559 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
560 break;
561 case MODE_UNDEFINED:
562 tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
563 if (ec(tc) != EC_UNKNOWN)
564 setSyndrome(tc, MISCREG_HSR);
565 break;
566 case MODE_HYP:
567 assert(have_virtualization);
568 tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr);
569 setSyndrome(tc, MISCREG_HSR);
570 break;
571 default:
572 panic("unknown Mode\n");
573 }
574
575 Addr newPc = getVector(tc);
576 DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
577 name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
578 PCState pc(newPc);
579 pc.thumb(cpsr.t);
580 pc.nextThumb(pc.thumb());
581 pc.jazelle(cpsr.j);
582 pc.nextJazelle(pc.jazelle());
583 pc.aarch64(!cpsr.width);
584 pc.nextAArch64(!cpsr.width);
585 tc->pcState(pc);
586 }
587
588 void
589 ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst)
590 {
591 // Determine actual misc. register indices for ELR_ELx and SPSR_ELx
592 MiscRegIndex elr_idx, spsr_idx;
593 switch (toEL) {
594 case EL1:
595 elr_idx = MISCREG_ELR_EL1;
596 spsr_idx = MISCREG_SPSR_EL1;
597 break;
598 case EL2:
599 assert(ArmSystem::haveVirtualization(tc));
600 elr_idx = MISCREG_ELR_EL2;
601 spsr_idx = MISCREG_SPSR_EL2;
602 break;
603 case EL3:
604 assert(ArmSystem::haveSecurity(tc));
605 elr_idx = MISCREG_ELR_EL3;
606 spsr_idx = MISCREG_SPSR_EL3;
607 break;
608 default:
609 panic("Invalid target exception level");
610 break;
611 }
612
613 // Save process state into SPSR_ELx
614 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
615 CPSR spsr = cpsr;
616 spsr.nz = tc->readCCReg(CCREG_NZ);
617 spsr.c = tc->readCCReg(CCREG_C);
618 spsr.v = tc->readCCReg(CCREG_V);
619 if (from64) {
620 // Force some bitfields to 0
621 spsr.q = 0;
622 spsr.it1 = 0;
623 spsr.j = 0;
624 spsr.res0_23_22 = 0;
625 spsr.ge = 0;
626 spsr.it2 = 0;
627 spsr.t = 0;
628 } else {
629 spsr.ge = tc->readCCReg(CCREG_GE);
630 ITSTATE it = tc->pcState().itstate();
631 spsr.it2 = it.top6;
632 spsr.it1 = it.bottom2;
633 // Force some bitfields to 0
634 spsr.res0_23_22 = 0;
635 spsr.ss = 0;
636 }
637 tc->setMiscReg(spsr_idx, spsr);
638
639 // Save preferred return address into ELR_ELx
640 Addr curr_pc = tc->pcState().pc();
641 Addr ret_addr = curr_pc;
642 if (from64)
643 ret_addr += armPcElrOffset();
644 else
645 ret_addr += spsr.t ? thumbPcElrOffset() : armPcElrOffset();
646 tc->setMiscReg(elr_idx, ret_addr);
647
648 // Update process state
649 OperatingMode64 mode = 0;
650 mode.spX = 1;
651 mode.el = toEL;
652 mode.width = 0;
653 cpsr.mode = mode;
654 cpsr.daif = 0xf;
655 cpsr.il = 0;
656 cpsr.ss = 0;
657 tc->setMiscReg(MISCREG_CPSR, cpsr);
658
659 // Set PC to start of exception handler
660 Addr new_pc = purifyTaggedAddr(getVector64(tc), tc, toEL);
661 DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x "
662 "elr:%#x newVec: %#x\n", name(), cpsr, curr_pc, ret_addr, new_pc);
663 PCState pc(new_pc);
664 pc.aarch64(!cpsr.width);
665 pc.nextAArch64(!cpsr.width);
666 tc->pcState(pc);
667
668 // If we have a valid instruction then use it to annotate this fault with
669 // extra information. This is used to generate the correct fault syndrome
670 // information
671 if (inst)
672 reinterpret_cast<ArmStaticInst *>(inst.get())->annotateFault(this);
673 // Save exception syndrome
674 if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ))
675 setSyndrome(tc, getSyndromeReg64());
676 }
677
678 void
679 Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
680 {
681 if (FullSystem) {
682 tc->getCpuPtr()->clearInterrupts(tc->threadId());
683 tc->clearArchRegs();
684 }
685 if (!ArmSystem::highestELIs64(tc)) {
686 ArmFault::invoke(tc, inst);
687 tc->setMiscReg(MISCREG_VMPIDR,
688 getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc));
689
690 // Unless we have SMC code to get us there, boot in HYP!
691 if (ArmSystem::haveVirtualization(tc) &&
692 !ArmSystem::haveSecurity(tc)) {
693 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
694 cpsr.mode = MODE_HYP;
695 tc->setMiscReg(MISCREG_CPSR, cpsr);
696 }
697 } else {
698 // Advance the PC to the IMPLEMENTATION DEFINED reset value
699 PCState pc = ArmSystem::resetAddr64(tc);
700 pc.aarch64(true);
701 pc.nextAArch64(true);
702 tc->pcState(pc);
703 }
704 }
705
706 void
707 UndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst)
708 {
709 if (FullSystem) {
710 ArmFault::invoke(tc, inst);
711 return;
712 }
713
714 // If the mnemonic isn't defined this has to be an unknown instruction.
715 assert(unknown || mnemonic != NULL);
716 if (disabled) {
717 panic("Attempted to execute disabled instruction "
718 "'%s' (inst 0x%08x)", mnemonic, machInst);
719 } else if (unknown) {
720 panic("Attempted to execute unknown instruction (inst 0x%08x)",
721 machInst);
722 } else {
723 panic("Attempted to execute unimplemented instruction "
724 "'%s' (inst 0x%08x)", mnemonic, machInst);
725 }
726 }
727
728 bool
729 UndefinedInstruction::routeToHyp(ThreadContext *tc) const
730 {
731 bool toHyp;
732
733 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
734 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
735 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
736
737 // if in Hyp mode then stay in Hyp mode
738 toHyp = scr.ns && (cpsr.mode == MODE_HYP);
739 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
740 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER);
741 return toHyp;
742 }
743
744 uint32_t
745 UndefinedInstruction::iss() const
746 {
747 if (overrideEc == EC_INVALID)
748 return issRaw;
749
750 uint32_t new_iss = 0;
751 uint32_t op0, op1, op2, CRn, CRm, Rt, dir;
752
753 dir = bits(machInst, 21, 21);
754 op0 = bits(machInst, 20, 19);
755 op1 = bits(machInst, 18, 16);
756 CRn = bits(machInst, 15, 12);
757 CRm = bits(machInst, 11, 8);
758 op2 = bits(machInst, 7, 5);
759 Rt = bits(machInst, 4, 0);
760
761 new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 |
762 Rt << 5 | CRm << 1 | dir;
763
764 return new_iss;
765 }
766
767 void
768 SupervisorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst)
769 {
770 if (FullSystem) {
771 ArmFault::invoke(tc, inst);
772 return;
773 }
774
775 // As of now, there isn't a 32 bit thumb version of this instruction.
776 assert(!machInst.bigThumb);
777 uint32_t callNum;
778 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
779 OperatingMode mode = (OperatingMode)(uint8_t)cpsr.mode;
780 if (opModeIs64(mode))
781 callNum = tc->readIntReg(INTREG_X8);
782 else
783 callNum = tc->readIntReg(INTREG_R7);
784 tc->syscall(callNum);
785
786 // Advance the PC since that won't happen automatically.
787 PCState pc = tc->pcState();
788 assert(inst);
789 inst->advancePC(pc);
790 tc->pcState(pc);
791 }
792
793 bool
794 SupervisorCall::routeToHyp(ThreadContext *tc) const
795 {
796 bool toHyp;
797
798 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
799 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
800 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
801
802 // if in Hyp mode then stay in Hyp mode
803 toHyp = scr.ns && (cpsr.mode == MODE_HYP);
804 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
805 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER);
806 return toHyp;
807 }
808
809 ExceptionClass
810 SupervisorCall::ec(ThreadContext *tc) const
811 {
812 return (overrideEc != EC_INVALID) ? overrideEc :
813 (from64 ? EC_SVC_64 : vals.ec);
814 }
815
816 uint32_t
817 SupervisorCall::iss() const
818 {
819 // Even if we have a 24 bit imm from an arm32 instruction then we only use
820 // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC).
821 return issRaw & 0xFFFF;
822 }
823
824 uint32_t
825 SecureMonitorCall::iss() const
826 {
827 if (from64)
828 return bits(machInst, 20, 5);
829 return 0;
830 }
831
832 ExceptionClass
833 UndefinedInstruction::ec(ThreadContext *tc) const
834 {
835 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
836 }
837
838
839 HypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) :
840 ArmFaultVals<HypervisorCall>(_machInst, _imm)
841 {}
842
843 ExceptionClass
844 HypervisorTrap::ec(ThreadContext *tc) const
845 {
846 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
847 }
848
849 template<class T>
850 FaultOffset
851 ArmFaultVals<T>::offset(ThreadContext *tc)
852 {
853 bool isHypTrap = false;
854
855 // Normally we just use the exception vector from the table at the top if
856 // this file, however if this exception has caused a transition to hype
857 // mode, and its an exception type that would only do this if it has been
858 // trapped then we use the hyp trap vector instead of the normal vector
859 if (vals.hypTrappable) {
860 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
861 if (cpsr.mode == MODE_HYP) {
862 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
863 isHypTrap = spsr.mode != MODE_HYP;
864 }
865 }
866 return isHypTrap ? 0x14 : vals.offset;
867 }
868
869 // void
870 // SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx)
871 // {
872 // ESR esr = 0;
873 // esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32;
874 // esr.il = !machInst.thumb;
875 // if (machInst.aarch64)
876 // esr.imm16 = bits(machInst.instBits, 20, 5);
877 // else if (machInst.thumb)
878 // esr.imm16 = bits(machInst.instBits, 7, 0);
879 // else
880 // esr.imm16 = bits(machInst.instBits, 15, 0);
881 // tc->setMiscReg(esr_idx, esr);
882 // }
883
884 void
885 SecureMonitorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst)
886 {
887 if (FullSystem) {
888 ArmFault::invoke(tc, inst);
889 return;
890 }
891 }
892
893 ExceptionClass
894 SecureMonitorCall::ec(ThreadContext *tc) const
895 {
896 return (from64 ? EC_SMC_64 : vals.ec);
897 }
898
899 ExceptionClass
900 SupervisorTrap::ec(ThreadContext *tc) const
901 {
902 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
903 }
904
905 ExceptionClass
906 SecureMonitorTrap::ec(ThreadContext *tc) const
907 {
908 return (overrideEc != EC_INVALID) ? overrideEc :
909 (from64 ? EC_SMC_64 : vals.ec);
910 }
911
912 template<class T>
913 void
914 AbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst)
915 {
916 if (tranMethod == ArmFault::UnknownTran) {
917 tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran
918 : ArmFault::VmsaTran;
919
920 if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) {
921 // See ARM ARM B3-1416
922 bool override_LPAE = false;
923 TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S);
924 TTBCR M5_VAR_USED ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS);
925 if (ttbcr_s.eae) {
926 override_LPAE = true;
927 } else {
928 // Unimplemented code option, not seen in testing. May need
929 // extension according to the manual exceprt above.
930 DPRINTF(Faults, "Warning: Incomplete translation method "
931 "override detected.\n");
932 }
933 if (override_LPAE)
934 tranMethod = ArmFault::LpaeTran;
935 }
936 }
937
938 if (source == ArmFault::AsynchronousExternalAbort) {
939 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
940 }
941 // Get effective fault source encoding
942 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
943 FSR fsr = getFsr(tc);
944
945 // source must be determined BEFORE invoking generic routines which will
946 // try to set hsr etc. and are based upon source!
947 ArmFaultVals<T>::invoke(tc, inst);
948
949 if (!this->to64) { // AArch32
950 if (cpsr.mode == MODE_HYP) {
951 tc->setMiscReg(T::HFarIndex, faultAddr);
952 } else if (stage2) {
953 tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf);
954 tc->setMiscReg(T::HFarIndex, OVAddr);
955 } else {
956 tc->setMiscReg(T::FsrIndex, fsr);
957 tc->setMiscReg(T::FarIndex, faultAddr);
958 }
959 DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\
960 "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod);
961 } else { // AArch64
962 // Set the FAR register. Nothing else to do if we are in AArch64 state
963 // because the syndrome register has already been set inside invoke64()
964 tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr);
965 }
966 }
967
968 template<class T>
969 FSR
970 AbortFault<T>::getFsr(ThreadContext *tc)
971 {
972 FSR fsr = 0;
973
974 if (((CPSR) tc->readMiscRegNoEffect(MISCREG_CPSR)).width) {
975 // AArch32
976 assert(tranMethod != ArmFault::UnknownTran);
977 if (tranMethod == ArmFault::LpaeTran) {
978 srcEncoded = ArmFault::longDescFaultSources[source];
979 fsr.status = srcEncoded;
980 fsr.lpae = 1;
981 } else {
982 srcEncoded = ArmFault::shortDescFaultSources[source];
983 fsr.fsLow = bits(srcEncoded, 3, 0);
984 fsr.fsHigh = bits(srcEncoded, 4);
985 fsr.domain = static_cast<uint8_t>(domain);
986 }
987 fsr.wnr = (write ? 1 : 0);
988 fsr.ext = 0;
989 } else {
990 // AArch64
991 srcEncoded = ArmFault::aarch64FaultSources[source];
992 }
993 if (srcEncoded == ArmFault::FaultSourceInvalid) {
994 panic("Invalid fault source\n");
995 }
996 return fsr;
997 }
998
999 template<class T>
1000 bool
1001 AbortFault<T>::abortDisable(ThreadContext *tc)
1002 {
1003 if (ArmSystem::haveSecurity(tc)) {
1004 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1005 return (!scr.ns || scr.aw);
1006 }
1007 return true;
1008 }
1009
1010 template<class T>
1011 void
1012 AbortFault<T>::annotate(ArmFault::AnnotationIDs id, uint64_t val)
1013 {
1014 switch (id)
1015 {
1016 case ArmFault::S1PTW:
1017 s1ptw = val;
1018 break;
1019 case ArmFault::OVA:
1020 OVAddr = val;
1021 break;
1022
1023 // Just ignore unknown ID's
1024 default:
1025 break;
1026 }
1027 }
1028
1029 template<class T>
1030 uint32_t
1031 AbortFault<T>::iss() const
1032 {
1033 uint32_t val;
1034
1035 val = srcEncoded & 0x3F;
1036 val |= write << 6;
1037 val |= s1ptw << 7;
1038 return (val);
1039 }
1040
1041 template<class T>
1042 bool
1043 AbortFault<T>::isMMUFault() const
1044 {
1045 // NOTE: Not relying on LL information being aligned to lowest bits here
1046 return
1047 (source == ArmFault::AlignmentFault) ||
1048 ((source >= ArmFault::TranslationLL) &&
1049 (source < ArmFault::TranslationLL + 4)) ||
1050 ((source >= ArmFault::AccessFlagLL) &&
1051 (source < ArmFault::AccessFlagLL + 4)) ||
1052 ((source >= ArmFault::DomainLL) &&
1053 (source < ArmFault::DomainLL + 4)) ||
1054 ((source >= ArmFault::PermissionLL) &&
1055 (source < ArmFault::PermissionLL + 4));
1056 }
1057
1058 ExceptionClass
1059 PrefetchAbort::ec(ThreadContext *tc) const
1060 {
1061 if (to64) {
1062 // AArch64
1063 if (toEL == fromEL)
1064 return EC_PREFETCH_ABORT_CURR_EL;
1065 else
1066 return EC_PREFETCH_ABORT_LOWER_EL;
1067 } else {
1068 // AArch32
1069 // Abort faults have different EC codes depending on whether
1070 // the fault originated within HYP mode, or not. So override
1071 // the method and add the extra adjustment of the EC value.
1072
1073 ExceptionClass ec = ArmFaultVals<PrefetchAbort>::vals.ec;
1074
1075 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
1076 if (spsr.mode == MODE_HYP) {
1077 ec = ((ExceptionClass) (((uint32_t) ec) + 1));
1078 }
1079 return ec;
1080 }
1081 }
1082
1083 bool
1084 PrefetchAbort::routeToMonitor(ThreadContext *tc) const
1085 {
1086 SCR scr = 0;
1087 if (from64)
1088 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1089 else
1090 scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1091
1092 return scr.ea && !isMMUFault();
1093 }
1094
1095 bool
1096 PrefetchAbort::routeToHyp(ThreadContext *tc) const
1097 {
1098 bool toHyp;
1099
1100 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1101 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1102 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1103 HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
1104
1105 // if in Hyp mode then stay in Hyp mode
1106 toHyp = scr.ns && (cpsr.mode == MODE_HYP);
1107 // otherwise, check whether to take to Hyp mode through Hyp Trap vector
1108 toHyp |= (stage2 ||
1109 ( (source == DebugEvent) && hdcr.tde && (cpsr.mode != MODE_HYP)) ||
1110 ( (source == SynchronousExternalAbort) && hcr.tge && (cpsr.mode == MODE_USER))
1111 ) && !inSecureState(scr, cpsr);
1112 return toHyp;
1113 }
1114
1115 ExceptionClass
1116 DataAbort::ec(ThreadContext *tc) const
1117 {
1118 if (to64) {
1119 // AArch64
1120 if (source == ArmFault::AsynchronousExternalAbort) {
1121 panic("Asynchronous External Abort should be handled with "
1122 "SystemErrors (SErrors)!");
1123 }
1124 if (toEL == fromEL)
1125 return EC_DATA_ABORT_CURR_EL;
1126 else
1127 return EC_DATA_ABORT_LOWER_EL;
1128 } else {
1129 // AArch32
1130 // Abort faults have different EC codes depending on whether
1131 // the fault originated within HYP mode, or not. So override
1132 // the method and add the extra adjustment of the EC value.
1133
1134 ExceptionClass ec = ArmFaultVals<DataAbort>::vals.ec;
1135
1136 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
1137 if (spsr.mode == MODE_HYP) {
1138 ec = ((ExceptionClass) (((uint32_t) ec) + 1));
1139 }
1140 return ec;
1141 }
1142 }
1143
1144 bool
1145 DataAbort::routeToMonitor(ThreadContext *tc) const
1146 {
1147 SCR scr = 0;
1148 if (from64)
1149 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1150 else
1151 scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1152
1153 return scr.ea && !isMMUFault();
1154 }
1155
1156 bool
1157 DataAbort::routeToHyp(ThreadContext *tc) const
1158 {
1159 bool toHyp;
1160
1161 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1162 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1163 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1164 HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
1165
1166 // if in Hyp mode then stay in Hyp mode
1167 toHyp = scr.ns && (cpsr.mode == MODE_HYP);
1168 // otherwise, check whether to take to Hyp mode through Hyp Trap vector
1169 toHyp |= (stage2 ||
1170 ( (cpsr.mode != MODE_HYP) && ( ((source == AsynchronousExternalAbort) && hcr.amo) ||
1171 ((source == DebugEvent) && hdcr.tde) )
1172 ) ||
1173 ( (cpsr.mode == MODE_USER) && hcr.tge &&
1174 ((source == AlignmentFault) ||
1175 (source == SynchronousExternalAbort))
1176 )
1177 ) && !inSecureState(scr, cpsr);
1178 return toHyp;
1179 }
1180
1181 uint32_t
1182 DataAbort::iss() const
1183 {
1184 uint32_t val;
1185
1186 // Add on the data abort specific fields to the generic abort ISS value
1187 val = AbortFault<DataAbort>::iss();
1188 // ISS is valid if not caused by a stage 1 page table walk, and when taken
1189 // to AArch64 only when directed to EL2
1190 if (!s1ptw && (!to64 || toEL == EL2)) {
1191 val |= isv << 24;
1192 if (isv) {
1193 val |= sas << 22;
1194 val |= sse << 21;
1195 val |= srt << 16;
1196 // AArch64 only. These assignments are safe on AArch32 as well
1197 // because these vars are initialized to false
1198 val |= sf << 15;
1199 val |= ar << 14;
1200 }
1201 }
1202 return (val);
1203 }
1204
1205 void
1206 DataAbort::annotate(AnnotationIDs id, uint64_t val)
1207 {
1208 AbortFault<DataAbort>::annotate(id, val);
1209 switch (id)
1210 {
1211 case SAS:
1212 isv = true;
1213 sas = val;
1214 break;
1215 case SSE:
1216 isv = true;
1217 sse = val;
1218 break;
1219 case SRT:
1220 isv = true;
1221 srt = val;
1222 break;
1223 case SF:
1224 isv = true;
1225 sf = val;
1226 break;
1227 case AR:
1228 isv = true;
1229 ar = val;
1230 break;
1231 // Just ignore unknown ID's
1232 default:
1233 break;
1234 }
1235 }
1236
1237 void
1238 VirtualDataAbort::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1239 {
1240 AbortFault<VirtualDataAbort>::invoke(tc, inst);
1241 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1242 hcr.va = 0;
1243 tc->setMiscRegNoEffect(MISCREG_HCR, hcr);
1244 }
1245
1246 bool
1247 Interrupt::routeToMonitor(ThreadContext *tc) const
1248 {
1249 assert(ArmSystem::haveSecurity(tc));
1250 SCR scr = 0;
1251 if (from64)
1252 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1253 else
1254 scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1255 return scr.irq;
1256 }
1257
1258 bool
1259 Interrupt::routeToHyp(ThreadContext *tc) const
1260 {
1261 bool toHyp;
1262
1263 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1264 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1265 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1266 // Determine whether IRQs are routed to Hyp mode.
1267 toHyp = (!scr.irq && hcr.imo && !inSecureState(scr, cpsr)) ||
1268 (cpsr.mode == MODE_HYP);
1269 return toHyp;
1270 }
1271
1272 bool
1273 Interrupt::abortDisable(ThreadContext *tc)
1274 {
1275 if (ArmSystem::haveSecurity(tc)) {
1276 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1277 return (!scr.ns || scr.aw);
1278 }
1279 return true;
1280 }
1281
1282 VirtualInterrupt::VirtualInterrupt()
1283 {}
1284
1285 bool
1286 FastInterrupt::routeToMonitor(ThreadContext *tc) const
1287 {
1288 assert(ArmSystem::haveSecurity(tc));
1289 SCR scr = 0;
1290 if (from64)
1291 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1292 else
1293 scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1294 return scr.fiq;
1295 }
1296
1297 bool
1298 FastInterrupt::routeToHyp(ThreadContext *tc) const
1299 {
1300 bool toHyp;
1301
1302 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1303 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1304 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1305 // Determine whether IRQs are routed to Hyp mode.
1306 toHyp = (!scr.fiq && hcr.fmo && !inSecureState(scr, cpsr)) ||
1307 (cpsr.mode == MODE_HYP);
1308 return toHyp;
1309 }
1310
1311 bool
1312 FastInterrupt::abortDisable(ThreadContext *tc)
1313 {
1314 if (ArmSystem::haveSecurity(tc)) {
1315 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1316 return (!scr.ns || scr.aw);
1317 }
1318 return true;
1319 }
1320
1321 bool
1322 FastInterrupt::fiqDisable(ThreadContext *tc)
1323 {
1324 if (ArmSystem::haveVirtualization(tc)) {
1325 return true;
1326 } else if (ArmSystem::haveSecurity(tc)) {
1327 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1328 return (!scr.ns || scr.fw);
1329 }
1330 return true;
1331 }
1332
1333 VirtualFastInterrupt::VirtualFastInterrupt()
1334 {}
1335
1336 void
1337 PCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1338 {
1339 ArmFaultVals<PCAlignmentFault>::invoke(tc, inst);
1340 assert(from64);
1341 // Set the FAR
1342 tc->setMiscReg(getFaultAddrReg64(), faultPC);
1343 }
1344
1345 SPAlignmentFault::SPAlignmentFault()
1346 {}
1347
1348 SystemError::SystemError()
1349 {}
1350
1351 void
1352 SystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1353 {
1354 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
1355 ArmFault::invoke(tc, inst);
1356 }
1357
1358 bool
1359 SystemError::routeToMonitor(ThreadContext *tc) const
1360 {
1361 assert(ArmSystem::haveSecurity(tc));
1362 assert(from64);
1363 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1364 return scr.ea;
1365 }
1366
1367 bool
1368 SystemError::routeToHyp(ThreadContext *tc) const
1369 {
1370 bool toHyp;
1371 assert(from64);
1372
1373 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1374 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1375 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1376
1377 toHyp = (!scr.ea && hcr.amo && !inSecureState(scr, cpsr)) ||
1378 (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(scr,cpsr));
1379 return toHyp;
1380 }
1381
1382 void
1383 FlushPipe::invoke(ThreadContext *tc, const StaticInstPtr &inst) {
1384 DPRINTF(Faults, "Invoking FlushPipe Fault\n");
1385
1386 // Set the PC to the next instruction of the faulting instruction.
1387 // Net effect is simply squashing all instructions behind and
1388 // start refetching from the next instruction.
1389 PCState pc = tc->pcState();
1390 assert(inst);
1391 inst->advancePC(pc);
1392 tc->pcState(pc);
1393 }
1394
1395 void
1396 ArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) {
1397 DPRINTF(Faults, "Invoking ArmSev Fault\n");
1398 if (!FullSystem)
1399 return;
1400
1401 // Set sev_mailbox to 1, clear the pending interrupt from remote
1402 // SEV execution and let pipeline continue as pcState is still
1403 // valid.
1404 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
1405 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0);
1406 }
1407
1408 // Instantiate all the templates to make the linker happy
1409 template class ArmFaultVals<Reset>;
1410 template class ArmFaultVals<UndefinedInstruction>;
1411 template class ArmFaultVals<SupervisorCall>;
1412 template class ArmFaultVals<SecureMonitorCall>;
1413 template class ArmFaultVals<HypervisorCall>;
1414 template class ArmFaultVals<PrefetchAbort>;
1415 template class ArmFaultVals<DataAbort>;
1416 template class ArmFaultVals<VirtualDataAbort>;
1417 template class ArmFaultVals<HypervisorTrap>;
1418 template class ArmFaultVals<Interrupt>;
1419 template class ArmFaultVals<VirtualInterrupt>;
1420 template class ArmFaultVals<FastInterrupt>;
1421 template class ArmFaultVals<VirtualFastInterrupt>;
1422 template class ArmFaultVals<SupervisorTrap>;
1423 template class ArmFaultVals<SecureMonitorTrap>;
1424 template class ArmFaultVals<PCAlignmentFault>;
1425 template class ArmFaultVals<SPAlignmentFault>;
1426 template class ArmFaultVals<SystemError>;
1427 template class ArmFaultVals<FlushPipe>;
1428 template class ArmFaultVals<ArmSev>;
1429 template class AbortFault<PrefetchAbort>;
1430 template class AbortFault<DataAbort>;
1431 template class AbortFault<VirtualDataAbort>;
1432
1433
1434 IllegalInstSetStateFault::IllegalInstSetStateFault()
1435 {}
1436
1437
1438 } // namespace ArmISA