src/arch/arm/faults.cc

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2007-2008 The Florida State University
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Ali Saidi
  42  *          Gabe Black
  43  */
  44
  45 #include "arch/arm/faults.hh"
  46 #include "cpu/thread_context.hh"
  47 #include "cpu/base.hh"
  48 #include "base/trace.hh"
  49
  50 namespace ArmISA
  51 {
  52
  53 template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals =
  54     {"reset", 0x00, MODE_SVC, 0, 0, true, true};
  55
  56 template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals =
  57     {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ;
  58
  59 template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals =
  60     {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false};
  61
  62 template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals =
  63     {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false};
  64
  65 template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals =
  66     {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false};
  67
  68 template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals =
  69     {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
  70
  71 template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals =
  72     {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
  73
  74 template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals =
  75     {"Pipe Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
  76
  77 template<> ArmFault::FaultVals ArmFaultVals<ReExec>::vals =
  78     {"ReExec Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
  79
  80 Addr
  81 ArmFault::getVector(ThreadContext *tc)
  82 {
  83     // ARM ARM B1-3
  84
  85     SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
  86
  87     // panic if SCTLR.VE because I have no idea what to do with vectored
  88     // interrupts
  89     assert(!sctlr.ve);
  90
  91     if (!sctlr.v)
  92         return offset();
  93     return offset() + HighVecs;
  94
  95 }
  96
  97 #if FULL_SYSTEM
  98
  99 void
 100 ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 101 {
 102     // ARM ARM B1.6.3
 103     FaultBase::invoke(tc);
 104     countStat()++;
 105
 106     SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
 107     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 108     CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
 109                       tc->readIntReg(INTREG_CONDCODES);
 110     Addr curPc M5_VAR_USED = tc->pcState().pc();
 111
 112
 113     cpsr.mode = nextMode();
 114     cpsr.it1 = cpsr.it2 = 0;
 115     cpsr.j = 0;
 116
 117     cpsr.t = sctlr.te;
 118     cpsr.a = cpsr.a | abortDisable();
 119     cpsr.f = cpsr.f | fiqDisable();
 120     cpsr.i = 1;
 121     cpsr.e = sctlr.ee;
 122     tc->setMiscReg(MISCREG_CPSR, cpsr);
 123     tc->setIntReg(INTREG_LR, curPc +
 124             (saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
 125
 126     switch (nextMode()) {
 127       case MODE_FIQ:
 128         tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
 129         break;
 130       case MODE_IRQ:
 131         tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
 132         break;
 133       case MODE_SVC:
 134         tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
 135         break;
 136       case MODE_UNDEFINED:
 137         tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
 138         break;
 139       case MODE_ABORT:
 140         tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
 141         break;
 142       default:
 143         panic("unknown Mode\n");
 144     }
 145
 146     Addr newPc = getVector(tc);
 147     DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
 148             name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
 149     PCState pc(newPc);
 150     pc.thumb(cpsr.t);
 151     pc.nextThumb(pc.thumb());
 152     pc.jazelle(cpsr.j);
 153     pc.nextJazelle(pc.jazelle());
 154     tc->pcState(pc);
 155 }
 156
 157 void
 158 Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
 159 {
 160     tc->getCpuPtr()->clearInterrupts();
 161     tc->clearArchRegs();
 162     ArmFault::invoke(tc);
 163 }
 164
 165 #else
 166
 167 void
 168 UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
 169 {
 170     // If the mnemonic isn't defined this has to be an unknown instruction.
 171     assert(unknown || mnemonic != NULL);
 172     if (disabled) {
 173         panic("Attempted to execute disabled instruction "
 174                 "'%s' (inst 0x%08x)", mnemonic, machInst);
 175     } else if (unknown) {
 176         panic("Attempted to execute unknown instruction (inst 0x%08x)",
 177               machInst);
 178     } else {
 179         panic("Attempted to execute unimplemented instruction "
 180                 "'%s' (inst 0x%08x)", mnemonic, machInst);
 181     }
 182 }
 183
 184 void
 185 SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
 186 {
 187     // As of now, there isn't a 32 bit thumb version of this instruction.
 188     assert(!machInst.bigThumb);
 189     uint32_t callNum;
 190     callNum = tc->readIntReg(INTREG_R7);
 191     tc->syscall(callNum);
 192
 193     // Advance the PC since that won't happen automatically.
 194     PCState pc = tc->pcState();
 195     assert(inst);
 196     inst->advancePC(pc);
 197     tc->pcState(pc);
 198 }
 199
 200 #endif // FULL_SYSTEM
 201
 202 template<class T>
 203 void
 204 AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
 205 {
 206     ArmFaultVals<T>::invoke(tc);
 207     FSR fsr = 0;
 208     fsr.fsLow = bits(status, 3, 0);
 209     fsr.fsHigh = bits(status, 4);
 210     fsr.domain = domain;
 211     fsr.wnr = (write ? 1 : 0);
 212     fsr.ext = 0;
 213     tc->setMiscReg(T::FsrIndex, fsr);
 214     tc->setMiscReg(T::FarIndex, faultAddr);
 215 }
 216
 217 void
 218 FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
 219     DPRINTF(Faults, "Invoking FlushPipe Fault\n");
 220
 221     // Set the PC to the next instruction of the faulting instruction.
 222     // Net effect is simply squashing all instructions behind and
 223     // start refetching from the next instruction.
 224     PCState pc = tc->pcState();
 225     assert(inst);
 226     pc.forcedItState(inst->machInst.newItstate);
 227     inst->advancePC(pc);
 228     tc->pcState(pc);
 229 }
 230
 231 void
 232 ReExec::invoke(ThreadContext *tc, StaticInstPtr inst) {
 233     DPRINTF(Faults, "Invoking ReExec Fault\n");
 234
 235     // Set the PC to then the faulting instruction.
 236     // Net effect is simply squashing all instructions including this
 237     // instruction and refetching/rexecuting current instruction
 238     PCState pc = tc->pcState();
 239     tc->pcState(pc);
 240 }
 241
 242 template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc,
 243                                                 StaticInstPtr inst);
 244 template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
 245                                             StaticInstPtr inst);
 246
 247 // return via SUBS pc, lr, xxx; rfe, movs, ldm
 248
 249 } // namespace ArmISA