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[gem5.git] / src / arch / arm / faults.cc
1 /*
2 * Copyright (c) 2010, 2012-2014, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 * Gabe Black
43 * Giacomo Gabrielli
44 * Thomas Grocutt
45 */
46
47 #include "arch/arm/faults.hh"
48
49 #include "arch/arm/insts/static_inst.hh"
50 #include "arch/arm/system.hh"
51 #include "arch/arm/utility.hh"
52 #include "base/compiler.hh"
53 #include "base/trace.hh"
54 #include "cpu/base.hh"
55 #include "cpu/thread_context.hh"
56 #include "debug/Faults.hh"
57 #include "sim/full_system.hh"
58
59 namespace ArmISA
60 {
61
62 uint8_t ArmFault::shortDescFaultSources[] = {
63 0x01, // AlignmentFault
64 0x04, // InstructionCacheMaintenance
65 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID)
66 0x0c, // SynchExtAbtOnTranslTableWalkL1
67 0x0e, // SynchExtAbtOnTranslTableWalkL2
68 0xff, // SynchExtAbtOnTranslTableWalkL3 (INVALID)
69 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID)
70 0x1c, // SynchPtyErrOnTranslTableWalkL1
71 0x1e, // SynchPtyErrOnTranslTableWalkL2
72 0xff, // SynchPtyErrOnTranslTableWalkL3 (INVALID)
73 0xff, // TranslationL0 (INVALID)
74 0x05, // TranslationL1
75 0x07, // TranslationL2
76 0xff, // TranslationL3 (INVALID)
77 0xff, // AccessFlagL0 (INVALID)
78 0x03, // AccessFlagL1
79 0x06, // AccessFlagL2
80 0xff, // AccessFlagL3 (INVALID)
81 0xff, // DomainL0 (INVALID)
82 0x09, // DomainL1
83 0x0b, // DomainL2
84 0xff, // DomainL3 (INVALID)
85 0xff, // PermissionL0 (INVALID)
86 0x0d, // PermissionL1
87 0x0f, // PermissionL2
88 0xff, // PermissionL3 (INVALID)
89 0x02, // DebugEvent
90 0x08, // SynchronousExternalAbort
91 0x10, // TLBConflictAbort
92 0x19, // SynchPtyErrOnMemoryAccess
93 0x16, // AsynchronousExternalAbort
94 0x18, // AsynchPtyErrOnMemoryAccess
95 0xff, // AddressSizeL0 (INVALID)
96 0xff, // AddressSizeL1 (INVALID)
97 0xff, // AddressSizeL2 (INVALID)
98 0xff, // AddressSizeL3 (INVALID)
99 0x40, // PrefetchTLBMiss
100 0x80 // PrefetchUncacheable
101 };
102
103 static_assert(sizeof(ArmFault::shortDescFaultSources) ==
104 ArmFault::NumFaultSources,
105 "Invalid size of ArmFault::shortDescFaultSources[]");
106
107 uint8_t ArmFault::longDescFaultSources[] = {
108 0x21, // AlignmentFault
109 0xff, // InstructionCacheMaintenance (INVALID)
110 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID)
111 0x15, // SynchExtAbtOnTranslTableWalkL1
112 0x16, // SynchExtAbtOnTranslTableWalkL2
113 0x17, // SynchExtAbtOnTranslTableWalkL3
114 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID)
115 0x1d, // SynchPtyErrOnTranslTableWalkL1
116 0x1e, // SynchPtyErrOnTranslTableWalkL2
117 0x1f, // SynchPtyErrOnTranslTableWalkL3
118 0xff, // TranslationL0 (INVALID)
119 0x05, // TranslationL1
120 0x06, // TranslationL2
121 0x07, // TranslationL3
122 0xff, // AccessFlagL0 (INVALID)
123 0x09, // AccessFlagL1
124 0x0a, // AccessFlagL2
125 0x0b, // AccessFlagL3
126 0xff, // DomainL0 (INVALID)
127 0x3d, // DomainL1
128 0x3e, // DomainL2
129 0xff, // DomainL3 (RESERVED)
130 0xff, // PermissionL0 (INVALID)
131 0x0d, // PermissionL1
132 0x0e, // PermissionL2
133 0x0f, // PermissionL3
134 0x22, // DebugEvent
135 0x10, // SynchronousExternalAbort
136 0x30, // TLBConflictAbort
137 0x18, // SynchPtyErrOnMemoryAccess
138 0x11, // AsynchronousExternalAbort
139 0x19, // AsynchPtyErrOnMemoryAccess
140 0xff, // AddressSizeL0 (INVALID)
141 0xff, // AddressSizeL1 (INVALID)
142 0xff, // AddressSizeL2 (INVALID)
143 0xff, // AddressSizeL3 (INVALID)
144 0x40, // PrefetchTLBMiss
145 0x80 // PrefetchUncacheable
146 };
147
148 static_assert(sizeof(ArmFault::longDescFaultSources) ==
149 ArmFault::NumFaultSources,
150 "Invalid size of ArmFault::longDescFaultSources[]");
151
152 uint8_t ArmFault::aarch64FaultSources[] = {
153 0x21, // AlignmentFault
154 0xff, // InstructionCacheMaintenance (INVALID)
155 0x14, // SynchExtAbtOnTranslTableWalkL0
156 0x15, // SynchExtAbtOnTranslTableWalkL1
157 0x16, // SynchExtAbtOnTranslTableWalkL2
158 0x17, // SynchExtAbtOnTranslTableWalkL3
159 0x1c, // SynchPtyErrOnTranslTableWalkL0
160 0x1d, // SynchPtyErrOnTranslTableWalkL1
161 0x1e, // SynchPtyErrOnTranslTableWalkL2
162 0x1f, // SynchPtyErrOnTranslTableWalkL3
163 0x04, // TranslationL0
164 0x05, // TranslationL1
165 0x06, // TranslationL2
166 0x07, // TranslationL3
167 0x08, // AccessFlagL0
168 0x09, // AccessFlagL1
169 0x0a, // AccessFlagL2
170 0x0b, // AccessFlagL3
171 // @todo: Section & Page Domain Fault in AArch64?
172 0xff, // DomainL0 (INVALID)
173 0xff, // DomainL1 (INVALID)
174 0xff, // DomainL2 (INVALID)
175 0xff, // DomainL3 (INVALID)
176 0x0c, // PermissionL0
177 0x0d, // PermissionL1
178 0x0e, // PermissionL2
179 0x0f, // PermissionL3
180 0xff, // DebugEvent (INVALID)
181 0x10, // SynchronousExternalAbort
182 0x30, // TLBConflictAbort
183 0x18, // SynchPtyErrOnMemoryAccess
184 0xff, // AsynchronousExternalAbort (INVALID)
185 0xff, // AsynchPtyErrOnMemoryAccess (INVALID)
186 0x00, // AddressSizeL0
187 0x01, // AddressSizeL1
188 0x02, // AddressSizeL2
189 0x03, // AddressSizeL3
190 0x40, // PrefetchTLBMiss
191 0x80 // PrefetchUncacheable
192 };
193
194 static_assert(sizeof(ArmFault::aarch64FaultSources) ==
195 ArmFault::NumFaultSources,
196 "Invalid size of ArmFault::aarch64FaultSources[]");
197
198 // Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode,
199 // {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap,
200 // {A, F} disable, class, stat
201 template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals = {
202 // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED
203 // location in AArch64)
204 "Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
205 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat()
206 };
207 template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals = {
208 "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED,
209 4, 2, 0, 0, true, false, false, EC_UNKNOWN, FaultStat()
210 };
211 template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals = {
212 "Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
213 4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP, FaultStat()
214 };
215 template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals = {
216 "Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON,
217 4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP, FaultStat()
218 };
219 template<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals = {
220 "Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
221 4, 4, 4, 4, true, false, false, EC_HVC, FaultStat()
222 };
223 template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals = {
224 "Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
225 4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP, FaultStat()
226 };
227 template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals = {
228 "Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
229 8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP, FaultStat()
230 };
231 template<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals = {
232 "Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
233 8, 8, 0, 0, true, true, false, EC_INVALID, FaultStat()
234 };
235 template<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals = {
236 // @todo: double check these values
237 "Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
238 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
239 };
240 template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals = {
241 "IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
242 4, 4, 0, 0, false, true, false, EC_UNKNOWN, FaultStat()
243 };
244 template<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals = {
245 "Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
246 4, 4, 0, 0, false, true, false, EC_INVALID, FaultStat()
247 };
248 template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals = {
249 "FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
250 4, 4, 0, 0, false, true, true, EC_UNKNOWN, FaultStat()
251 };
252 template<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals = {
253 "Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
254 4, 4, 0, 0, false, true, true, EC_INVALID, FaultStat()
255 };
256 template<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals = {
257 // Some dummy values (SupervisorTrap is AArch64-only)
258 "Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
259 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
260 };
261 template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals = {
262 // Some dummy values (SecureMonitorTrap is AArch64-only)
263 "Secure Monitor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_MON,
264 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat()
265 };
266 template<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals = {
267 // Some dummy values (PCAlignmentFault is AArch64-only)
268 "PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
269 0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT, FaultStat()
270 };
271 template<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals = {
272 // Some dummy values (SPAlignmentFault is AArch64-only)
273 "SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
274 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT, FaultStat()
275 };
276 template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals = {
277 // Some dummy values (SError is AArch64-only)
278 "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC,
279 0, 0, 0, 0, false, true, true, EC_SERROR, FaultStat()
280 };
281 template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals = {
282 // Some dummy values
283 "Pipe Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
284 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat()
285 };
286 template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals = {
287 // Some dummy values
288 "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
289 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat()
290 };
291 template<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals = {
292 // Some dummy values (SPAlignmentFault is AArch64-only)
293 "Illegal Inst Set State Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
294 0, 0, 0, 0, true, false, false, EC_ILLEGAL_INST, FaultStat()
295 };
296
297 Addr
298 ArmFault::getVector(ThreadContext *tc)
299 {
300 Addr base;
301
302 // ARM ARM issue C B1.8.1
303 bool haveSecurity = ArmSystem::haveSecurity(tc);
304
305 // panic if SCTLR.VE because I have no idea what to do with vectored
306 // interrupts
307 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
308 assert(!sctlr.ve);
309 // Check for invalid modes
310 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
311 assert(haveSecurity || cpsr.mode != MODE_MON);
312 assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
313
314 switch (cpsr.mode)
315 {
316 case MODE_MON:
317 base = tc->readMiscReg(MISCREG_MVBAR);
318 break;
319 case MODE_HYP:
320 base = tc->readMiscReg(MISCREG_HVBAR);
321 break;
322 default:
323 if (sctlr.v) {
324 base = HighVecs;
325 } else {
326 base = haveSecurity ? tc->readMiscReg(MISCREG_VBAR) : 0;
327 }
328 break;
329 }
330 return base + offset(tc);
331 }
332
333 Addr
334 ArmFault::getVector64(ThreadContext *tc)
335 {
336 Addr vbar;
337 switch (toEL) {
338 case EL3:
339 assert(ArmSystem::haveSecurity(tc));
340 vbar = tc->readMiscReg(MISCREG_VBAR_EL3);
341 break;
342 case EL2:
343 assert(ArmSystem::haveVirtualization(tc));
344 vbar = tc->readMiscReg(MISCREG_VBAR_EL2);
345 break;
346 case EL1:
347 vbar = tc->readMiscReg(MISCREG_VBAR_EL1);
348 break;
349 default:
350 panic("Invalid target exception level");
351 break;
352 }
353 return vbar + offset64();
354 }
355
356 MiscRegIndex
357 ArmFault::getSyndromeReg64() const
358 {
359 switch (toEL) {
360 case EL1:
361 return MISCREG_ESR_EL1;
362 case EL2:
363 return MISCREG_ESR_EL2;
364 case EL3:
365 return MISCREG_ESR_EL3;
366 default:
367 panic("Invalid exception level");
368 break;
369 }
370 }
371
372 MiscRegIndex
373 ArmFault::getFaultAddrReg64() const
374 {
375 switch (toEL) {
376 case EL1:
377 return MISCREG_FAR_EL1;
378 case EL2:
379 return MISCREG_FAR_EL2;
380 case EL3:
381 return MISCREG_FAR_EL3;
382 default:
383 panic("Invalid exception level");
384 break;
385 }
386 }
387
388 void
389 ArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
390 {
391 uint32_t value;
392 uint32_t exc_class = (uint32_t) ec(tc);
393 uint32_t issVal = iss();
394 assert(!from64 || ArmSystem::highestELIs64(tc));
395
396 value = exc_class << 26;
397
398 // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24,
399 // 0x25) for which the ISS information is not valid (ARMv7).
400 // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not
401 // valid it is treated as RES1.
402 if (to64) {
403 value |= 1 << 25;
404 } else if ((bits(exc_class, 5, 3) != 4) ||
405 (bits(exc_class, 2) && bits(issVal, 24))) {
406 if (!machInst.thumb || machInst.bigThumb)
407 value |= 1 << 25;
408 }
409 // Condition code valid for EC[5:4] nonzero
410 if (!from64 && ((bits(exc_class, 5, 4) == 0) &&
411 (bits(exc_class, 3, 0) != 0))) {
412 if (!machInst.thumb) {
413 uint32_t cond;
414 ConditionCode condCode = (ConditionCode) (uint32_t) machInst.condCode;
415 // If its on unconditional instruction report with a cond code of
416 // 0xE, ie the unconditional code
417 cond = (condCode == COND_UC) ? COND_AL : condCode;
418 value |= cond << 20;
419 value |= 1 << 24;
420 }
421 value |= bits(issVal, 19, 0);
422 } else {
423 value |= issVal;
424 }
425 tc->setMiscReg(syndrome_reg, value);
426 }
427
428 void
429 ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
430 {
431 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
432
433 if (ArmSystem::highestELIs64(tc)) { // ARMv8
434 // Determine source exception level and mode
435 fromMode = (OperatingMode) (uint8_t) cpsr.mode;
436 fromEL = opModeToEL(fromMode);
437 if (opModeIs64(fromMode))
438 from64 = true;
439
440 // Determine target exception level
441 if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc))
442 toEL = EL3;
443 else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc))
444 toEL = EL2;
445 else
446 toEL = opModeToEL(nextMode());
447 if (fromEL > toEL)
448 toEL = fromEL;
449
450 if (toEL == ArmSystem::highestEL(tc) || ELIs64(tc, toEL)) {
451 // Invoke exception handler in AArch64 state
452 to64 = true;
453 invoke64(tc, inst);
454 return;
455 }
456 }
457
458 // ARMv7 (ARM ARM issue C B1.9)
459
460 bool have_security = ArmSystem::haveSecurity(tc);
461 bool have_virtualization = ArmSystem::haveVirtualization(tc);
462
463 FaultBase::invoke(tc);
464 if (!FullSystem)
465 return;
466 countStat()++;
467
468 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
469 SCR scr = tc->readMiscReg(MISCREG_SCR);
470 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR);
471 saved_cpsr.nz = tc->readCCReg(CCREG_NZ);
472 saved_cpsr.c = tc->readCCReg(CCREG_C);
473 saved_cpsr.v = tc->readCCReg(CCREG_V);
474 saved_cpsr.ge = tc->readCCReg(CCREG_GE);
475
476 Addr curPc M5_VAR_USED = tc->pcState().pc();
477 ITSTATE it = tc->pcState().itstate();
478 saved_cpsr.it2 = it.top6;
479 saved_cpsr.it1 = it.bottom2;
480
481 // if we have a valid instruction then use it to annotate this fault with
482 // extra information. This is used to generate the correct fault syndrome
483 // information
484 if (inst) {
485 ArmStaticInst *armInst = reinterpret_cast<ArmStaticInst *>(inst.get());
486 armInst->annotateFault(this);
487 }
488
489 if (have_security && routeToMonitor(tc))
490 cpsr.mode = MODE_MON;
491 else if (have_virtualization && routeToHyp(tc))
492 cpsr.mode = MODE_HYP;
493 else
494 cpsr.mode = nextMode();
495
496 // Ensure Secure state if initially in Monitor mode
497 if (have_security && saved_cpsr.mode == MODE_MON) {
498 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
499 if (scr.ns) {
500 scr.ns = 0;
501 tc->setMiscRegNoEffect(MISCREG_SCR, scr);
502 }
503 }
504
505 // some bits are set differently if we have been routed to hyp mode
506 if (cpsr.mode == MODE_HYP) {
507 SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR);
508 cpsr.t = hsctlr.te;
509 cpsr.e = hsctlr.ee;
510 if (!scr.ea) {cpsr.a = 1;}
511 if (!scr.fiq) {cpsr.f = 1;}
512 if (!scr.irq) {cpsr.i = 1;}
513 } else if (cpsr.mode == MODE_MON) {
514 // Special case handling when entering monitor mode
515 cpsr.t = sctlr.te;
516 cpsr.e = sctlr.ee;
517 cpsr.a = 1;
518 cpsr.f = 1;
519 cpsr.i = 1;
520 } else {
521 cpsr.t = sctlr.te;
522 cpsr.e = sctlr.ee;
523
524 // The *Disable functions are virtual and different per fault
525 cpsr.a = cpsr.a | abortDisable(tc);
526 cpsr.f = cpsr.f | fiqDisable(tc);
527 cpsr.i = 1;
528 }
529 cpsr.it1 = cpsr.it2 = 0;
530 cpsr.j = 0;
531 tc->setMiscReg(MISCREG_CPSR, cpsr);
532
533 // Make sure mailbox sets to one always
534 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
535
536 // Clear the exclusive monitor
537 tc->setMiscReg(MISCREG_LOCKFLAG, 0);
538
539 if (cpsr.mode == MODE_HYP) {
540 tc->setMiscReg(MISCREG_ELR_HYP, curPc +
541 (saved_cpsr.t ? thumbPcOffset(true) : armPcOffset(true)));
542 } else {
543 tc->setIntReg(INTREG_LR, curPc +
544 (saved_cpsr.t ? thumbPcOffset(false) : armPcOffset(false)));
545 }
546
547 switch (cpsr.mode) {
548 case MODE_FIQ:
549 tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
550 break;
551 case MODE_IRQ:
552 tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
553 break;
554 case MODE_SVC:
555 tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
556 break;
557 case MODE_MON:
558 assert(have_security);
559 tc->setMiscReg(MISCREG_SPSR_MON, saved_cpsr);
560 break;
561 case MODE_ABORT:
562 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
563 break;
564 case MODE_UNDEFINED:
565 tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
566 if (ec(tc) != EC_UNKNOWN)
567 setSyndrome(tc, MISCREG_HSR);
568 break;
569 case MODE_HYP:
570 assert(have_virtualization);
571 tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr);
572 setSyndrome(tc, MISCREG_HSR);
573 break;
574 default:
575 panic("unknown Mode\n");
576 }
577
578 Addr newPc = getVector(tc);
579 DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
580 name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
581 PCState pc(newPc);
582 pc.thumb(cpsr.t);
583 pc.nextThumb(pc.thumb());
584 pc.jazelle(cpsr.j);
585 pc.nextJazelle(pc.jazelle());
586 pc.aarch64(!cpsr.width);
587 pc.nextAArch64(!cpsr.width);
588 tc->pcState(pc);
589 }
590
591 void
592 ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst)
593 {
594 // Determine actual misc. register indices for ELR_ELx and SPSR_ELx
595 MiscRegIndex elr_idx, spsr_idx;
596 switch (toEL) {
597 case EL1:
598 elr_idx = MISCREG_ELR_EL1;
599 spsr_idx = MISCREG_SPSR_EL1;
600 break;
601 case EL2:
602 assert(ArmSystem::haveVirtualization(tc));
603 elr_idx = MISCREG_ELR_EL2;
604 spsr_idx = MISCREG_SPSR_EL2;
605 break;
606 case EL3:
607 assert(ArmSystem::haveSecurity(tc));
608 elr_idx = MISCREG_ELR_EL3;
609 spsr_idx = MISCREG_SPSR_EL3;
610 break;
611 default:
612 panic("Invalid target exception level");
613 break;
614 }
615
616 // Save process state into SPSR_ELx
617 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
618 CPSR spsr = cpsr;
619 spsr.nz = tc->readCCReg(CCREG_NZ);
620 spsr.c = tc->readCCReg(CCREG_C);
621 spsr.v = tc->readCCReg(CCREG_V);
622 if (from64) {
623 // Force some bitfields to 0
624 spsr.q = 0;
625 spsr.it1 = 0;
626 spsr.j = 0;
627 spsr.res0_23_22 = 0;
628 spsr.ge = 0;
629 spsr.it2 = 0;
630 spsr.t = 0;
631 } else {
632 spsr.ge = tc->readCCReg(CCREG_GE);
633 ITSTATE it = tc->pcState().itstate();
634 spsr.it2 = it.top6;
635 spsr.it1 = it.bottom2;
636 // Force some bitfields to 0
637 spsr.res0_23_22 = 0;
638 spsr.ss = 0;
639 }
640 tc->setMiscReg(spsr_idx, spsr);
641
642 // Save preferred return address into ELR_ELx
643 Addr curr_pc = tc->pcState().pc();
644 Addr ret_addr = curr_pc;
645 if (from64)
646 ret_addr += armPcElrOffset();
647 else
648 ret_addr += spsr.t ? thumbPcElrOffset() : armPcElrOffset();
649 tc->setMiscReg(elr_idx, ret_addr);
650
651 // Update process state
652 OperatingMode64 mode = 0;
653 mode.spX = 1;
654 mode.el = toEL;
655 mode.width = 0;
656 cpsr.mode = mode;
657 cpsr.daif = 0xf;
658 cpsr.il = 0;
659 cpsr.ss = 0;
660 tc->setMiscReg(MISCREG_CPSR, cpsr);
661
662 // Set PC to start of exception handler
663 Addr new_pc = purifyTaggedAddr(getVector64(tc), tc, toEL);
664 DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x "
665 "elr:%#x newVec: %#x\n", name(), cpsr, curr_pc, ret_addr, new_pc);
666 PCState pc(new_pc);
667 pc.aarch64(!cpsr.width);
668 pc.nextAArch64(!cpsr.width);
669 tc->pcState(pc);
670
671 // If we have a valid instruction then use it to annotate this fault with
672 // extra information. This is used to generate the correct fault syndrome
673 // information
674 if (inst)
675 reinterpret_cast<ArmStaticInst *>(inst.get())->annotateFault(this);
676 // Save exception syndrome
677 if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ))
678 setSyndrome(tc, getSyndromeReg64());
679 }
680
681 void
682 Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
683 {
684 if (FullSystem) {
685 tc->getCpuPtr()->clearInterrupts(tc->threadId());
686 tc->clearArchRegs();
687 }
688 if (!ArmSystem::highestELIs64(tc)) {
689 ArmFault::invoke(tc, inst);
690 tc->setMiscReg(MISCREG_VMPIDR,
691 getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc));
692
693 // Unless we have SMC code to get us there, boot in HYP!
694 if (ArmSystem::haveVirtualization(tc) &&
695 !ArmSystem::haveSecurity(tc)) {
696 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
697 cpsr.mode = MODE_HYP;
698 tc->setMiscReg(MISCREG_CPSR, cpsr);
699 }
700 } else {
701 // Advance the PC to the IMPLEMENTATION DEFINED reset value
702 PCState pc = ArmSystem::resetAddr64(tc);
703 pc.aarch64(true);
704 pc.nextAArch64(true);
705 tc->pcState(pc);
706 }
707 }
708
709 void
710 UndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst)
711 {
712 if (FullSystem) {
713 ArmFault::invoke(tc, inst);
714 return;
715 }
716
717 // If the mnemonic isn't defined this has to be an unknown instruction.
718 assert(unknown || mnemonic != NULL);
719 if (disabled) {
720 panic("Attempted to execute disabled instruction "
721 "'%s' (inst 0x%08x)", mnemonic, machInst);
722 } else if (unknown) {
723 panic("Attempted to execute unknown instruction (inst 0x%08x)",
724 machInst);
725 } else {
726 panic("Attempted to execute unimplemented instruction "
727 "'%s' (inst 0x%08x)", mnemonic, machInst);
728 }
729 }
730
731 bool
732 UndefinedInstruction::routeToHyp(ThreadContext *tc) const
733 {
734 bool toHyp;
735
736 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
737 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
738 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
739
740 // if in Hyp mode then stay in Hyp mode
741 toHyp = scr.ns && (cpsr.mode == MODE_HYP);
742 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
743 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER);
744 return toHyp;
745 }
746
747 uint32_t
748 UndefinedInstruction::iss() const
749 {
750 if (overrideEc == EC_INVALID)
751 return issRaw;
752
753 uint32_t new_iss = 0;
754 uint32_t op0, op1, op2, CRn, CRm, Rt, dir;
755
756 dir = bits(machInst, 21, 21);
757 op0 = bits(machInst, 20, 19);
758 op1 = bits(machInst, 18, 16);
759 CRn = bits(machInst, 15, 12);
760 CRm = bits(machInst, 11, 8);
761 op2 = bits(machInst, 7, 5);
762 Rt = bits(machInst, 4, 0);
763
764 new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 |
765 Rt << 5 | CRm << 1 | dir;
766
767 return new_iss;
768 }
769
770 void
771 SupervisorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst)
772 {
773 if (FullSystem) {
774 ArmFault::invoke(tc, inst);
775 return;
776 }
777
778 // As of now, there isn't a 32 bit thumb version of this instruction.
779 assert(!machInst.bigThumb);
780 uint32_t callNum;
781 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
782 OperatingMode mode = (OperatingMode)(uint8_t)cpsr.mode;
783 if (opModeIs64(mode))
784 callNum = tc->readIntReg(INTREG_X8);
785 else
786 callNum = tc->readIntReg(INTREG_R7);
787 tc->syscall(callNum);
788
789 // Advance the PC since that won't happen automatically.
790 PCState pc = tc->pcState();
791 assert(inst);
792 inst->advancePC(pc);
793 tc->pcState(pc);
794 }
795
796 bool
797 SupervisorCall::routeToHyp(ThreadContext *tc) const
798 {
799 bool toHyp;
800
801 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
802 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
803 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
804
805 // if in Hyp mode then stay in Hyp mode
806 toHyp = scr.ns && (cpsr.mode == MODE_HYP);
807 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
808 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER);
809 return toHyp;
810 }
811
812 ExceptionClass
813 SupervisorCall::ec(ThreadContext *tc) const
814 {
815 return (overrideEc != EC_INVALID) ? overrideEc :
816 (from64 ? EC_SVC_64 : vals.ec);
817 }
818
819 uint32_t
820 SupervisorCall::iss() const
821 {
822 // Even if we have a 24 bit imm from an arm32 instruction then we only use
823 // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC).
824 return issRaw & 0xFFFF;
825 }
826
827 uint32_t
828 SecureMonitorCall::iss() const
829 {
830 if (from64)
831 return bits(machInst, 20, 5);
832 return 0;
833 }
834
835 ExceptionClass
836 UndefinedInstruction::ec(ThreadContext *tc) const
837 {
838 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
839 }
840
841
842 HypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) :
843 ArmFaultVals<HypervisorCall>(_machInst, _imm)
844 {}
845
846 ExceptionClass
847 HypervisorCall::ec(ThreadContext *tc) const
848 {
849 return from64 ? EC_HVC_64 : vals.ec;
850 }
851
852 ExceptionClass
853 HypervisorTrap::ec(ThreadContext *tc) const
854 {
855 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
856 }
857
858 template<class T>
859 FaultOffset
860 ArmFaultVals<T>::offset(ThreadContext *tc)
861 {
862 bool isHypTrap = false;
863
864 // Normally we just use the exception vector from the table at the top if
865 // this file, however if this exception has caused a transition to hype
866 // mode, and its an exception type that would only do this if it has been
867 // trapped then we use the hyp trap vector instead of the normal vector
868 if (vals.hypTrappable) {
869 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
870 if (cpsr.mode == MODE_HYP) {
871 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
872 isHypTrap = spsr.mode != MODE_HYP;
873 }
874 }
875 return isHypTrap ? 0x14 : vals.offset;
876 }
877
878 // void
879 // SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx)
880 // {
881 // ESR esr = 0;
882 // esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32;
883 // esr.il = !machInst.thumb;
884 // if (machInst.aarch64)
885 // esr.imm16 = bits(machInst.instBits, 20, 5);
886 // else if (machInst.thumb)
887 // esr.imm16 = bits(machInst.instBits, 7, 0);
888 // else
889 // esr.imm16 = bits(machInst.instBits, 15, 0);
890 // tc->setMiscReg(esr_idx, esr);
891 // }
892
893 void
894 SecureMonitorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst)
895 {
896 if (FullSystem) {
897 ArmFault::invoke(tc, inst);
898 return;
899 }
900 }
901
902 ExceptionClass
903 SecureMonitorCall::ec(ThreadContext *tc) const
904 {
905 return (from64 ? EC_SMC_64 : vals.ec);
906 }
907
908 ExceptionClass
909 SupervisorTrap::ec(ThreadContext *tc) const
910 {
911 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
912 }
913
914 ExceptionClass
915 SecureMonitorTrap::ec(ThreadContext *tc) const
916 {
917 return (overrideEc != EC_INVALID) ? overrideEc :
918 (from64 ? EC_SMC_64 : vals.ec);
919 }
920
921 template<class T>
922 void
923 AbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst)
924 {
925 if (tranMethod == ArmFault::UnknownTran) {
926 tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran
927 : ArmFault::VmsaTran;
928
929 if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) {
930 // See ARM ARM B3-1416
931 bool override_LPAE = false;
932 TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S);
933 TTBCR M5_VAR_USED ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS);
934 if (ttbcr_s.eae) {
935 override_LPAE = true;
936 } else {
937 // Unimplemented code option, not seen in testing. May need
938 // extension according to the manual exceprt above.
939 DPRINTF(Faults, "Warning: Incomplete translation method "
940 "override detected.\n");
941 }
942 if (override_LPAE)
943 tranMethod = ArmFault::LpaeTran;
944 }
945 }
946
947 if (source == ArmFault::AsynchronousExternalAbort) {
948 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
949 }
950 // Get effective fault source encoding
951 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
952 FSR fsr = getFsr(tc);
953
954 // source must be determined BEFORE invoking generic routines which will
955 // try to set hsr etc. and are based upon source!
956 ArmFaultVals<T>::invoke(tc, inst);
957
958 if (!this->to64) { // AArch32
959 if (cpsr.mode == MODE_HYP) {
960 tc->setMiscReg(T::HFarIndex, faultAddr);
961 } else if (stage2) {
962 tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf);
963 tc->setMiscReg(T::HFarIndex, OVAddr);
964 } else {
965 tc->setMiscReg(T::FsrIndex, fsr);
966 tc->setMiscReg(T::FarIndex, faultAddr);
967 }
968 DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\
969 "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod);
970 } else { // AArch64
971 // Set the FAR register. Nothing else to do if we are in AArch64 state
972 // because the syndrome register has already been set inside invoke64()
973 if (stage2) {
974 // stage 2 fault, set HPFAR_EL2 to the faulting IPA
975 // and FAR_EL2 to the Original VA
976 tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), OVAddr);
977 tc->setMiscReg(MISCREG_HPFAR_EL2, bits(faultAddr, 47, 12) << 4);
978
979 DPRINTF(Faults, "Abort Fault (Stage 2) VA: 0x%x IPA: 0x%x\n",
980 OVAddr, faultAddr);
981 } else {
982 tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr);
983 }
984 }
985 }
986
987 template<class T>
988 FSR
989 AbortFault<T>::getFsr(ThreadContext *tc)
990 {
991 FSR fsr = 0;
992
993 if (((CPSR) tc->readMiscRegNoEffect(MISCREG_CPSR)).width) {
994 // AArch32
995 assert(tranMethod != ArmFault::UnknownTran);
996 if (tranMethod == ArmFault::LpaeTran) {
997 srcEncoded = ArmFault::longDescFaultSources[source];
998 fsr.status = srcEncoded;
999 fsr.lpae = 1;
1000 } else {
1001 srcEncoded = ArmFault::shortDescFaultSources[source];
1002 fsr.fsLow = bits(srcEncoded, 3, 0);
1003 fsr.fsHigh = bits(srcEncoded, 4);
1004 fsr.domain = static_cast<uint8_t>(domain);
1005 }
1006 fsr.wnr = (write ? 1 : 0);
1007 fsr.ext = 0;
1008 } else {
1009 // AArch64
1010 srcEncoded = ArmFault::aarch64FaultSources[source];
1011 }
1012 if (srcEncoded == ArmFault::FaultSourceInvalid) {
1013 panic("Invalid fault source\n");
1014 }
1015 return fsr;
1016 }
1017
1018 template<class T>
1019 bool
1020 AbortFault<T>::abortDisable(ThreadContext *tc)
1021 {
1022 if (ArmSystem::haveSecurity(tc)) {
1023 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1024 return (!scr.ns || scr.aw);
1025 }
1026 return true;
1027 }
1028
1029 template<class T>
1030 void
1031 AbortFault<T>::annotate(ArmFault::AnnotationIDs id, uint64_t val)
1032 {
1033 switch (id)
1034 {
1035 case ArmFault::S1PTW:
1036 s1ptw = val;
1037 break;
1038 case ArmFault::OVA:
1039 OVAddr = val;
1040 break;
1041
1042 // Just ignore unknown ID's
1043 default:
1044 break;
1045 }
1046 }
1047
1048 template<class T>
1049 uint32_t
1050 AbortFault<T>::iss() const
1051 {
1052 uint32_t val;
1053
1054 val = srcEncoded & 0x3F;
1055 val |= write << 6;
1056 val |= s1ptw << 7;
1057 return (val);
1058 }
1059
1060 template<class T>
1061 bool
1062 AbortFault<T>::isMMUFault() const
1063 {
1064 // NOTE: Not relying on LL information being aligned to lowest bits here
1065 return
1066 (source == ArmFault::AlignmentFault) ||
1067 ((source >= ArmFault::TranslationLL) &&
1068 (source < ArmFault::TranslationLL + 4)) ||
1069 ((source >= ArmFault::AccessFlagLL) &&
1070 (source < ArmFault::AccessFlagLL + 4)) ||
1071 ((source >= ArmFault::DomainLL) &&
1072 (source < ArmFault::DomainLL + 4)) ||
1073 ((source >= ArmFault::PermissionLL) &&
1074 (source < ArmFault::PermissionLL + 4));
1075 }
1076
1077 ExceptionClass
1078 PrefetchAbort::ec(ThreadContext *tc) const
1079 {
1080 if (to64) {
1081 // AArch64
1082 if (toEL == fromEL)
1083 return EC_PREFETCH_ABORT_CURR_EL;
1084 else
1085 return EC_PREFETCH_ABORT_LOWER_EL;
1086 } else {
1087 // AArch32
1088 // Abort faults have different EC codes depending on whether
1089 // the fault originated within HYP mode, or not. So override
1090 // the method and add the extra adjustment of the EC value.
1091
1092 ExceptionClass ec = ArmFaultVals<PrefetchAbort>::vals.ec;
1093
1094 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
1095 if (spsr.mode == MODE_HYP) {
1096 ec = ((ExceptionClass) (((uint32_t) ec) + 1));
1097 }
1098 return ec;
1099 }
1100 }
1101
1102 bool
1103 PrefetchAbort::routeToMonitor(ThreadContext *tc) const
1104 {
1105 SCR scr = 0;
1106 if (from64)
1107 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1108 else
1109 scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1110
1111 return scr.ea && !isMMUFault();
1112 }
1113
1114 bool
1115 PrefetchAbort::routeToHyp(ThreadContext *tc) const
1116 {
1117 bool toHyp;
1118
1119 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1120 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1121 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1122 HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
1123
1124 // if in Hyp mode then stay in Hyp mode
1125 toHyp = scr.ns && (cpsr.mode == MODE_HYP);
1126 // otherwise, check whether to take to Hyp mode through Hyp Trap vector
1127 toHyp |= (stage2 ||
1128 ( (source == DebugEvent) && hdcr.tde && (cpsr.mode != MODE_HYP)) ||
1129 ( (source == SynchronousExternalAbort) && hcr.tge && (cpsr.mode == MODE_USER))
1130 ) && !inSecureState(tc);
1131 return toHyp;
1132 }
1133
1134 ExceptionClass
1135 DataAbort::ec(ThreadContext *tc) const
1136 {
1137 if (to64) {
1138 // AArch64
1139 if (source == ArmFault::AsynchronousExternalAbort) {
1140 panic("Asynchronous External Abort should be handled with "
1141 "SystemErrors (SErrors)!");
1142 }
1143 if (toEL == fromEL)
1144 return EC_DATA_ABORT_CURR_EL;
1145 else
1146 return EC_DATA_ABORT_LOWER_EL;
1147 } else {
1148 // AArch32
1149 // Abort faults have different EC codes depending on whether
1150 // the fault originated within HYP mode, or not. So override
1151 // the method and add the extra adjustment of the EC value.
1152
1153 ExceptionClass ec = ArmFaultVals<DataAbort>::vals.ec;
1154
1155 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
1156 if (spsr.mode == MODE_HYP) {
1157 ec = ((ExceptionClass) (((uint32_t) ec) + 1));
1158 }
1159 return ec;
1160 }
1161 }
1162
1163 bool
1164 DataAbort::routeToMonitor(ThreadContext *tc) const
1165 {
1166 SCR scr = 0;
1167 if (from64)
1168 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1169 else
1170 scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1171
1172 return scr.ea && !isMMUFault();
1173 }
1174
1175 bool
1176 DataAbort::routeToHyp(ThreadContext *tc) const
1177 {
1178 bool toHyp;
1179
1180 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1181 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1182 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1183 HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
1184
1185 // if in Hyp mode then stay in Hyp mode
1186 toHyp = scr.ns && (cpsr.mode == MODE_HYP);
1187 // otherwise, check whether to take to Hyp mode through Hyp Trap vector
1188 toHyp |= (stage2 ||
1189 ( (cpsr.mode != MODE_HYP) && ( ((source == AsynchronousExternalAbort) && hcr.amo) ||
1190 ((source == DebugEvent) && hdcr.tde) )
1191 ) ||
1192 ( (cpsr.mode == MODE_USER) && hcr.tge &&
1193 ((source == AlignmentFault) ||
1194 (source == SynchronousExternalAbort))
1195 )
1196 ) && !inSecureState(tc);
1197 return toHyp;
1198 }
1199
1200 uint32_t
1201 DataAbort::iss() const
1202 {
1203 uint32_t val;
1204
1205 // Add on the data abort specific fields to the generic abort ISS value
1206 val = AbortFault<DataAbort>::iss();
1207 // ISS is valid if not caused by a stage 1 page table walk, and when taken
1208 // to AArch64 only when directed to EL2
1209 if (!s1ptw && (!to64 || toEL == EL2)) {
1210 val |= isv << 24;
1211 if (isv) {
1212 val |= sas << 22;
1213 val |= sse << 21;
1214 val |= srt << 16;
1215 // AArch64 only. These assignments are safe on AArch32 as well
1216 // because these vars are initialized to false
1217 val |= sf << 15;
1218 val |= ar << 14;
1219 }
1220 }
1221 return (val);
1222 }
1223
1224 void
1225 DataAbort::annotate(AnnotationIDs id, uint64_t val)
1226 {
1227 AbortFault<DataAbort>::annotate(id, val);
1228 switch (id)
1229 {
1230 case SAS:
1231 isv = true;
1232 sas = val;
1233 break;
1234 case SSE:
1235 isv = true;
1236 sse = val;
1237 break;
1238 case SRT:
1239 isv = true;
1240 srt = val;
1241 break;
1242 case SF:
1243 isv = true;
1244 sf = val;
1245 break;
1246 case AR:
1247 isv = true;
1248 ar = val;
1249 break;
1250 // Just ignore unknown ID's
1251 default:
1252 break;
1253 }
1254 }
1255
1256 void
1257 VirtualDataAbort::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1258 {
1259 AbortFault<VirtualDataAbort>::invoke(tc, inst);
1260 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1261 hcr.va = 0;
1262 tc->setMiscRegNoEffect(MISCREG_HCR, hcr);
1263 }
1264
1265 bool
1266 Interrupt::routeToMonitor(ThreadContext *tc) const
1267 {
1268 assert(ArmSystem::haveSecurity(tc));
1269 SCR scr = 0;
1270 if (from64)
1271 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1272 else
1273 scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1274 return scr.irq;
1275 }
1276
1277 bool
1278 Interrupt::routeToHyp(ThreadContext *tc) const
1279 {
1280 bool toHyp;
1281
1282 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1283 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1284 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1285 // Determine whether IRQs are routed to Hyp mode.
1286 toHyp = (!scr.irq && hcr.imo && !inSecureState(tc)) ||
1287 (cpsr.mode == MODE_HYP);
1288 return toHyp;
1289 }
1290
1291 bool
1292 Interrupt::abortDisable(ThreadContext *tc)
1293 {
1294 if (ArmSystem::haveSecurity(tc)) {
1295 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1296 return (!scr.ns || scr.aw);
1297 }
1298 return true;
1299 }
1300
1301 VirtualInterrupt::VirtualInterrupt()
1302 {}
1303
1304 bool
1305 FastInterrupt::routeToMonitor(ThreadContext *tc) const
1306 {
1307 assert(ArmSystem::haveSecurity(tc));
1308 SCR scr = 0;
1309 if (from64)
1310 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1311 else
1312 scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1313 return scr.fiq;
1314 }
1315
1316 bool
1317 FastInterrupt::routeToHyp(ThreadContext *tc) const
1318 {
1319 bool toHyp;
1320
1321 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1322 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1323 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1324 // Determine whether IRQs are routed to Hyp mode.
1325 toHyp = (!scr.fiq && hcr.fmo && !inSecureState(tc)) ||
1326 (cpsr.mode == MODE_HYP);
1327 return toHyp;
1328 }
1329
1330 bool
1331 FastInterrupt::abortDisable(ThreadContext *tc)
1332 {
1333 if (ArmSystem::haveSecurity(tc)) {
1334 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1335 return (!scr.ns || scr.aw);
1336 }
1337 return true;
1338 }
1339
1340 bool
1341 FastInterrupt::fiqDisable(ThreadContext *tc)
1342 {
1343 if (ArmSystem::haveVirtualization(tc)) {
1344 return true;
1345 } else if (ArmSystem::haveSecurity(tc)) {
1346 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1347 return (!scr.ns || scr.fw);
1348 }
1349 return true;
1350 }
1351
1352 VirtualFastInterrupt::VirtualFastInterrupt()
1353 {}
1354
1355 void
1356 PCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1357 {
1358 ArmFaultVals<PCAlignmentFault>::invoke(tc, inst);
1359 assert(from64);
1360 // Set the FAR
1361 tc->setMiscReg(getFaultAddrReg64(), faultPC);
1362 }
1363
1364 SPAlignmentFault::SPAlignmentFault()
1365 {}
1366
1367 SystemError::SystemError()
1368 {}
1369
1370 void
1371 SystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1372 {
1373 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
1374 ArmFault::invoke(tc, inst);
1375 }
1376
1377 bool
1378 SystemError::routeToMonitor(ThreadContext *tc) const
1379 {
1380 assert(ArmSystem::haveSecurity(tc));
1381 assert(from64);
1382 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1383 return scr.ea;
1384 }
1385
1386 bool
1387 SystemError::routeToHyp(ThreadContext *tc) const
1388 {
1389 bool toHyp;
1390 assert(from64);
1391
1392 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1393 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1394
1395 toHyp = (!scr.ea && hcr.amo && !inSecureState(tc)) ||
1396 (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(tc));
1397 return toHyp;
1398 }
1399
1400 void
1401 FlushPipe::invoke(ThreadContext *tc, const StaticInstPtr &inst) {
1402 DPRINTF(Faults, "Invoking FlushPipe Fault\n");
1403
1404 // Set the PC to the next instruction of the faulting instruction.
1405 // Net effect is simply squashing all instructions behind and
1406 // start refetching from the next instruction.
1407 PCState pc = tc->pcState();
1408 assert(inst);
1409 inst->advancePC(pc);
1410 tc->pcState(pc);
1411 }
1412
1413 void
1414 ArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) {
1415 DPRINTF(Faults, "Invoking ArmSev Fault\n");
1416 if (!FullSystem)
1417 return;
1418
1419 // Set sev_mailbox to 1, clear the pending interrupt from remote
1420 // SEV execution and let pipeline continue as pcState is still
1421 // valid.
1422 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
1423 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0);
1424 }
1425
1426 // Instantiate all the templates to make the linker happy
1427 template class ArmFaultVals<Reset>;
1428 template class ArmFaultVals<UndefinedInstruction>;
1429 template class ArmFaultVals<SupervisorCall>;
1430 template class ArmFaultVals<SecureMonitorCall>;
1431 template class ArmFaultVals<HypervisorCall>;
1432 template class ArmFaultVals<PrefetchAbort>;
1433 template class ArmFaultVals<DataAbort>;
1434 template class ArmFaultVals<VirtualDataAbort>;
1435 template class ArmFaultVals<HypervisorTrap>;
1436 template class ArmFaultVals<Interrupt>;
1437 template class ArmFaultVals<VirtualInterrupt>;
1438 template class ArmFaultVals<FastInterrupt>;
1439 template class ArmFaultVals<VirtualFastInterrupt>;
1440 template class ArmFaultVals<SupervisorTrap>;
1441 template class ArmFaultVals<SecureMonitorTrap>;
1442 template class ArmFaultVals<PCAlignmentFault>;
1443 template class ArmFaultVals<SPAlignmentFault>;
1444 template class ArmFaultVals<SystemError>;
1445 template class ArmFaultVals<FlushPipe>;
1446 template class ArmFaultVals<ArmSev>;
1447 template class AbortFault<PrefetchAbort>;
1448 template class AbortFault<DataAbort>;
1449 template class AbortFault<VirtualDataAbort>;
1450
1451
1452 IllegalInstSetStateFault::IllegalInstSetStateFault()
1453 {}
1454
1455
1456 } // namespace ArmISA