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45 #include "arch/arm/faults.hh"
46 #include "base/trace.hh"
47 #include "cpu/base.hh"
48 #include "cpu/thread_context.hh"
49 #include "debug/Faults.hh"
50 #include "sim/full_system.hh"
55 template<> ArmFault::FaultVals ArmFaultVals
<Reset
>::vals
=
56 {"reset", 0x00, MODE_SVC
, 0, 0, true, true, FaultStat()};
58 template<> ArmFault::FaultVals ArmFaultVals
<UndefinedInstruction
>::vals
=
59 {"Undefined Instruction", 0x04, MODE_UNDEFINED
, 4 ,2, false, false,
62 template<> ArmFault::FaultVals ArmFaultVals
<SupervisorCall
>::vals
=
63 {"Supervisor Call", 0x08, MODE_SVC
, 4, 2, false, false, FaultStat()};
65 template<> ArmFault::FaultVals ArmFaultVals
<PrefetchAbort
>::vals
=
66 {"Prefetch Abort", 0x0C, MODE_ABORT
, 4, 4, true, false, FaultStat()};
68 template<> ArmFault::FaultVals ArmFaultVals
<DataAbort
>::vals
=
69 {"Data Abort", 0x10, MODE_ABORT
, 8, 8, true, false, FaultStat()};
71 template<> ArmFault::FaultVals ArmFaultVals
<Interrupt
>::vals
=
72 {"IRQ", 0x18, MODE_IRQ
, 4, 4, true, false, FaultStat()};
74 template<> ArmFault::FaultVals ArmFaultVals
<FastInterrupt
>::vals
=
75 {"FIQ", 0x1C, MODE_FIQ
, 4, 4, true, true, FaultStat()};
77 template<> ArmFault::FaultVals ArmFaultVals
<FlushPipe
>::vals
=
78 {"Pipe Flush", 0x00, MODE_SVC
, 0, 0, true, true, FaultStat()}; // dummy values
80 template<> ArmFault::FaultVals ArmFaultVals
<ArmSev
>::vals
=
81 {"ArmSev Flush", 0x00, MODE_SVC
, 0, 0, true, true, FaultStat()}; // dummy values
83 ArmFault::getVector(ThreadContext
*tc
)
87 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR
);
89 // panic if SCTLR.VE because I have no idea what to do with vectored
95 return offset() + HighVecs
;
100 ArmFault::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
103 FaultBase::invoke(tc
);
108 SCTLR sctlr
= tc
->readMiscReg(MISCREG_SCTLR
);
109 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
110 CPSR saved_cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
111 saved_cpsr
.nz
= tc
->readIntReg(INTREG_CONDCODES_NZ
);
112 saved_cpsr
.c
= tc
->readIntReg(INTREG_CONDCODES_C
);
113 saved_cpsr
.v
= tc
->readIntReg(INTREG_CONDCODES_V
);
114 saved_cpsr
.ge
= tc
->readIntReg(INTREG_CONDCODES_GE
);
116 Addr curPc M5_VAR_USED
= tc
->pcState().pc();
117 ITSTATE it
= tc
->pcState().itstate();
118 saved_cpsr
.it2
= it
.top6
;
119 saved_cpsr
.it1
= it
.bottom2
;
121 cpsr
.mode
= nextMode();
122 cpsr
.it1
= cpsr
.it2
= 0;
126 cpsr
.a
= cpsr
.a
| abortDisable();
127 cpsr
.f
= cpsr
.f
| fiqDisable();
130 tc
->setMiscReg(MISCREG_CPSR
, cpsr
);
131 // Make sure mailbox sets to one always
132 tc
->setMiscReg(MISCREG_SEV_MAILBOX
, 1);
133 tc
->setIntReg(INTREG_LR
, curPc
+
134 (saved_cpsr
.t
? thumbPcOffset() : armPcOffset()));
136 switch (nextMode()) {
138 tc
->setMiscReg(MISCREG_SPSR_FIQ
, saved_cpsr
);
141 tc
->setMiscReg(MISCREG_SPSR_IRQ
, saved_cpsr
);
144 tc
->setMiscReg(MISCREG_SPSR_SVC
, saved_cpsr
);
147 tc
->setMiscReg(MISCREG_SPSR_UND
, saved_cpsr
);
150 tc
->setMiscReg(MISCREG_SPSR_ABT
, saved_cpsr
);
153 panic("unknown Mode\n");
156 Addr newPc
= getVector(tc
);
157 DPRINTF(Faults
, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
158 name(), cpsr
, curPc
, tc
->readIntReg(INTREG_LR
), newPc
);
161 pc
.nextThumb(pc
.thumb());
163 pc
.nextJazelle(pc
.jazelle());
168 Reset::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
171 tc
->getCpuPtr()->clearInterrupts();
174 ArmFault::invoke(tc
, inst
);
178 UndefinedInstruction::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
181 ArmFault::invoke(tc
, inst
);
185 // If the mnemonic isn't defined this has to be an unknown instruction.
186 assert(unknown
|| mnemonic
!= NULL
);
188 panic("Attempted to execute disabled instruction "
189 "'%s' (inst 0x%08x)", mnemonic
, machInst
);
190 } else if (unknown
) {
191 panic("Attempted to execute unknown instruction (inst 0x%08x)",
194 panic("Attempted to execute unimplemented instruction "
195 "'%s' (inst 0x%08x)", mnemonic
, machInst
);
200 SupervisorCall::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
203 ArmFault::invoke(tc
, inst
);
207 // As of now, there isn't a 32 bit thumb version of this instruction.
208 assert(!machInst
.bigThumb
);
210 callNum
= tc
->readIntReg(INTREG_R7
);
211 tc
->syscall(callNum
);
213 // Advance the PC since that won't happen automatically.
214 PCState pc
= tc
->pcState();
222 AbortFault
<T
>::invoke(ThreadContext
*tc
, StaticInstPtr inst
)
224 ArmFaultVals
<T
>::invoke(tc
, inst
);
226 fsr
.fsLow
= bits(status
, 3, 0);
227 fsr
.fsHigh
= bits(status
, 4);
229 fsr
.wnr
= (write
? 1 : 0);
231 tc
->setMiscReg(T::FsrIndex
, fsr
);
232 tc
->setMiscReg(T::FarIndex
, faultAddr
);
234 DPRINTF(Faults
, "Abort Fault fsr=%#x faultAddr=%#x\n", fsr
, faultAddr
);
238 FlushPipe::invoke(ThreadContext
*tc
, StaticInstPtr inst
) {
239 DPRINTF(Faults
, "Invoking FlushPipe Fault\n");
241 // Set the PC to the next instruction of the faulting instruction.
242 // Net effect is simply squashing all instructions behind and
243 // start refetching from the next instruction.
244 PCState pc
= tc
->pcState();
250 template void AbortFault
<PrefetchAbort
>::invoke(ThreadContext
*tc
,
252 template void AbortFault
<DataAbort
>::invoke(ThreadContext
*tc
,
256 ArmSev::invoke(ThreadContext
*tc
, StaticInstPtr inst
) {
257 DPRINTF(Faults
, "Invoking ArmSev Fault\n");
261 // Set sev_mailbox to 1, clear the pending interrupt from remote
262 // SEV execution and let pipeline continue as pcState is still
264 tc
->setMiscReg(MISCREG_SEV_MAILBOX
, 1);
265 tc
->getCpuPtr()->clearInterrupt(INT_SEV
, 0);
268 // return via SUBS pc, lr, xxx; rfe, movs, ldm
270 } // namespace ArmISA