src/arch/arm/faults.hh

   1 /*
   2  * Copyright (c) 2010, 2012-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2007-2008 The Florida State University
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Ali Saidi
  42  *          Gabe Black
  43  *          Giacomo Gabrielli
  44  *          Thomas Grocutt
  45  */
  46
  47 #ifndef __ARM_FAULTS_HH__
  48 #define __ARM_FAULTS_HH__
  49
  50 #include "arch/arm/miscregs.hh"
  51 #include "arch/arm/pagetable.hh"
  52 #include "arch/arm/types.hh"
  53 #include "base/misc.hh"
  54 #include "sim/faults.hh"
  55 #include "sim/full_system.hh"
  56
  57 // The design of the "name" and "vect" functions is in sim/faults.hh
  58
  59 namespace ArmISA
  60 {
  61 typedef const Addr FaultOffset;
  62
  63 class ArmFault : public FaultBase
  64 {
  65   protected:
  66     ExtMachInst machInst;
  67     uint32_t issRaw;
  68
  69     // Helper variables for ARMv8 exception handling
  70     bool from64;  // True if the exception is generated from the AArch64 state
  71     bool to64;  // True if the exception is taken in AArch64 state
  72     ExceptionLevel fromEL;  // Source exception level
  73     ExceptionLevel toEL;  // Target exception level
  74     OperatingMode fromMode;  // Source operating mode
  75
  76     Addr getVector(ThreadContext *tc);
  77     Addr getVector64(ThreadContext *tc);
  78
  79   public:
  80     /// Generic fault source enums used to index into
  81     /// {short/long/aarch64}DescFaultSources[] to get the actual encodings based
  82     /// on the current register width state and the translation table format in
  83     /// use
  84     enum FaultSource
  85     {
  86         AlignmentFault = 0,
  87         InstructionCacheMaintenance,  // Short-desc. format only
  88         SynchExtAbtOnTranslTableWalkLL,
  89         SynchPtyErrOnTranslTableWalkLL = SynchExtAbtOnTranslTableWalkLL + 4,
  90         TranslationLL = SynchPtyErrOnTranslTableWalkLL + 4,
  91         AccessFlagLL = TranslationLL + 4,
  92         DomainLL = AccessFlagLL + 4,
  93         PermissionLL = DomainLL + 4,
  94         DebugEvent = PermissionLL + 4,
  95         SynchronousExternalAbort,
  96         TLBConflictAbort,  // Requires LPAE
  97         SynchPtyErrOnMemoryAccess,
  98         AsynchronousExternalAbort,
  99         AsynchPtyErrOnMemoryAccess,
 100         AddressSizeLL,  // AArch64 only
 101
 102         // Not real faults. These are faults to allow the translation function
 103         // to inform the memory access function not to proceed for a prefetch
 104         // that misses in the TLB or that targets an uncacheable address
 105         PrefetchTLBMiss = AddressSizeLL + 4,
 106         PrefetchUncacheable,
 107
 108         NumFaultSources,
 109         FaultSourceInvalid = 0xff
 110     };
 111
 112     /// Encodings of the fault sources when the short-desc. translation table
 113     /// format is in use (ARM ARM Issue C B3.13.3)
 114     static uint8_t shortDescFaultSources[NumFaultSources];
 115     /// Encodings of the fault sources when the long-desc. translation table
 116     /// format is in use (ARM ARM Issue C B3.13.3)
 117     static uint8_t longDescFaultSources[NumFaultSources];
 118     /// Encodings of the fault sources in AArch64 state
 119     static uint8_t aarch64FaultSources[NumFaultSources];
 120
 121     enum AnnotationIDs
 122     {
 123         S1PTW, // DataAbort, PrefetchAbort: Stage 1 Page Table Walk,
 124         OVA,   // DataAbort, PrefetchAbort: stage 1 Virtual Address for stage 2 faults
 125         SAS,   // DataAbort: Syndrome Access Size
 126         SSE,   // DataAbort: Syndrome Sign Extend
 127         SRT,   // DataAbort: Syndrome Register Transfer
 128
 129         // AArch64 only
 130         SF,    // DataAbort: width of the accessed register is SixtyFour
 131         AR     // DataAbort: Acquire/Release semantics
 132     };
 133
 134     enum TranMethod
 135     {
 136         LpaeTran,
 137         VmsaTran,
 138         UnknownTran
 139     };
 140
 141     struct FaultVals
 142     {
 143         const FaultName name;
 144
 145         const FaultOffset offset;
 146
 147         // Offsets used for exceptions taken in AArch64 state
 148         const uint16_t currELTOffset;
 149         const uint16_t currELHOffset;
 150         const uint16_t lowerEL64Offset;
 151         const uint16_t lowerEL32Offset;
 152
 153         const OperatingMode nextMode;
 154
 155         const uint8_t armPcOffset;
 156         const uint8_t thumbPcOffset;
 157         // The following two values are used in place of armPcOffset and
 158         // thumbPcOffset when the exception return address is saved into ELR
 159         // registers (exceptions taken in HYP mode or in AArch64 state)
 160         const uint8_t armPcElrOffset;
 161         const uint8_t thumbPcElrOffset;
 162
 163         const bool hypTrappable;
 164         const bool abortDisable;
 165         const bool fiqDisable;
 166
 167         // Exception class used to appropriately set the syndrome register
 168         // (exceptions taken in HYP mode or in AArch64 state)
 169         const ExceptionClass ec;
 170
 171         FaultStat count;
 172     };
 173
 174     ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
 175         machInst(_machInst), issRaw(_iss), from64(false), to64(false) {}
 176
 177     // Returns the actual syndrome register to use based on the target
 178     // exception level
 179     MiscRegIndex getSyndromeReg64() const;
 180     // Returns the actual fault address register to use based on the target
 181     // exception level
 182     MiscRegIndex getFaultAddrReg64() const;
 183
 184     void invoke(ThreadContext *tc, const StaticInstPtr &inst =
 185                 StaticInst::nullStaticInstPtr);
 186     void invoke64(ThreadContext *tc, const StaticInstPtr &inst =
 187                   StaticInst::nullStaticInstPtr);
 188     virtual void annotate(AnnotationIDs id, uint64_t val) {}
 189     virtual FaultStat& countStat() = 0;
 190     virtual FaultOffset offset(ThreadContext *tc) = 0;
 191     virtual FaultOffset offset64() = 0;
 192     virtual OperatingMode nextMode() = 0;
 193     virtual bool routeToMonitor(ThreadContext *tc) const = 0;
 194     virtual bool routeToHyp(ThreadContext *tc) const { return false; }
 195     virtual uint8_t armPcOffset(bool isHyp) = 0;
 196     virtual uint8_t thumbPcOffset(bool isHyp) = 0;
 197     virtual uint8_t armPcElrOffset() = 0;
 198     virtual uint8_t thumbPcElrOffset() = 0;
 199     virtual bool abortDisable(ThreadContext *tc) = 0;
 200     virtual bool fiqDisable(ThreadContext *tc) = 0;
 201     virtual ExceptionClass ec(ThreadContext *tc) const = 0;
 202     virtual uint32_t iss() const = 0;
 203     virtual bool isStage2() const { return false; }
 204     virtual FSR getFsr(ThreadContext *tc) { return 0; }
 205     virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
 206 };
 207
 208 template<typename T>
 209 class ArmFaultVals : public ArmFault
 210 {
 211   protected:
 212     static FaultVals vals;
 213
 214   public:
 215     ArmFaultVals<T>(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
 216         ArmFault(_machInst, _iss) {}
 217     FaultName name() const { return vals.name; }
 218     FaultStat & countStat() { return vals.count; }
 219     FaultOffset offset(ThreadContext *tc);
 220
 221     FaultOffset
 222     offset64()
 223     {
 224         if (toEL == fromEL) {
 225             if (opModeIsT(fromMode))
 226                 return vals.currELTOffset;
 227             return vals.currELHOffset;
 228         } else {
 229             if (from64)
 230                 return vals.lowerEL64Offset;
 231             return vals.lowerEL32Offset;
 232         }
 233     }
 234
 235     OperatingMode nextMode() { return vals.nextMode; }
 236     virtual bool routeToMonitor(ThreadContext *tc) const { return false; }
 237     uint8_t armPcOffset(bool isHyp)   { return isHyp ? vals.armPcElrOffset
 238                                                      : vals.armPcOffset; }
 239     uint8_t thumbPcOffset(bool isHyp) { return isHyp ? vals.thumbPcElrOffset
 240                                                      : vals.thumbPcOffset; }
 241     uint8_t armPcElrOffset() { return vals.armPcElrOffset; }
 242     uint8_t thumbPcElrOffset() { return vals.thumbPcElrOffset; }
 243     virtual bool abortDisable(ThreadContext* tc) { return vals.abortDisable; }
 244     virtual bool fiqDisable(ThreadContext* tc) { return vals.fiqDisable; }
 245     virtual ExceptionClass ec(ThreadContext *tc) const { return vals.ec; }
 246     virtual uint32_t iss() const { return issRaw; }
 247 };
 248
 249 class Reset : public ArmFaultVals<Reset>
 250 {
 251   public:
 252     void invoke(ThreadContext *tc, const StaticInstPtr &inst =
 253                 StaticInst::nullStaticInstPtr);
 254 };
 255
 256 class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
 257 {
 258   protected:
 259     bool unknown;
 260     bool disabled;
 261     ExceptionClass overrideEc;
 262     const char *mnemonic;
 263
 264   public:
 265     UndefinedInstruction(ExtMachInst _machInst,
 266                          bool _unknown,
 267                          const char *_mnemonic = NULL,
 268                          bool _disabled = false) :
 269         ArmFaultVals<UndefinedInstruction>(_machInst),
 270         unknown(_unknown), disabled(_disabled),
 271         overrideEc(EC_INVALID), mnemonic(_mnemonic)
 272     {}
 273     UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss,
 274             ExceptionClass _overrideEc, const char *_mnemonic = NULL) :
 275         ArmFaultVals<UndefinedInstruction>(_machInst, _iss),
 276         unknown(false), disabled(true), overrideEc(_overrideEc),
 277         mnemonic(_mnemonic)
 278     {}
 279
 280     void invoke(ThreadContext *tc, const StaticInstPtr &inst =
 281                 StaticInst::nullStaticInstPtr);
 282     bool routeToHyp(ThreadContext *tc) const;
 283     ExceptionClass ec(ThreadContext *tc) const;
 284     uint32_t iss() const;
 285 };
 286
 287 class SupervisorCall : public ArmFaultVals<SupervisorCall>
 288 {
 289   protected:
 290     ExceptionClass overrideEc;
 291   public:
 292     SupervisorCall(ExtMachInst _machInst, uint32_t _iss,
 293                    ExceptionClass _overrideEc = EC_INVALID) :
 294         ArmFaultVals<SupervisorCall>(_machInst, _iss),
 295         overrideEc(_overrideEc)
 296     {}
 297
 298     void invoke(ThreadContext *tc, const StaticInstPtr &inst =
 299                 StaticInst::nullStaticInstPtr);
 300     bool routeToHyp(ThreadContext *tc) const;
 301     ExceptionClass ec(ThreadContext *tc) const;
 302     uint32_t iss() const;
 303 };
 304
 305 class SecureMonitorCall : public ArmFaultVals<SecureMonitorCall>
 306 {
 307   public:
 308     SecureMonitorCall(ExtMachInst _machInst) :
 309         ArmFaultVals<SecureMonitorCall>(_machInst)
 310     {}
 311
 312     void invoke(ThreadContext *tc, const StaticInstPtr &inst =
 313                 StaticInst::nullStaticInstPtr);
 314     ExceptionClass ec(ThreadContext *tc) const;
 315     uint32_t iss() const;
 316 };
 317
 318 class SupervisorTrap : public ArmFaultVals<SupervisorTrap>
 319 {
 320   protected:
 321     ExtMachInst machInst;
 322     ExceptionClass overrideEc;
 323
 324   public:
 325     SupervisorTrap(ExtMachInst _machInst, uint32_t _iss,
 326                    ExceptionClass _overrideEc = EC_INVALID) :
 327         ArmFaultVals<SupervisorTrap>(_machInst, _iss),
 328         overrideEc(_overrideEc)
 329     {}
 330
 331     ExceptionClass ec(ThreadContext *tc) const;
 332 };
 333
 334 class SecureMonitorTrap : public ArmFaultVals<SecureMonitorTrap>
 335 {
 336  protected:
 337     ExtMachInst machInst;
 338     ExceptionClass overrideEc;
 339
 340   public:
 341     SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss,
 342                       ExceptionClass _overrideEc = EC_INVALID) :
 343         ArmFaultVals<SecureMonitorTrap>(_machInst, _iss),
 344         overrideEc(_overrideEc)
 345     {}
 346
 347     ExceptionClass ec(ThreadContext *tc) const;
 348 };
 349
 350 class HypervisorCall : public ArmFaultVals<HypervisorCall>
 351 {
 352   public:
 353     HypervisorCall(ExtMachInst _machInst, uint32_t _imm);
 354 };
 355
 356 class HypervisorTrap : public ArmFaultVals<HypervisorTrap>
 357 {
 358   protected:
 359     ExtMachInst machInst;
 360     ExceptionClass overrideEc;
 361
 362   public:
 363     HypervisorTrap(ExtMachInst _machInst, uint32_t _iss,
 364                    ExceptionClass _overrideEc = EC_INVALID) :
 365       ArmFaultVals<HypervisorTrap>(_machInst, _iss),
 366       overrideEc(_overrideEc)
 367     {}
 368
 369     ExceptionClass ec(ThreadContext *tc) const;
 370 };
 371
 372 template <class T>
 373 class AbortFault : public ArmFaultVals<T>
 374 {
 375   protected:
 376     /**
 377      * The virtual address the fault occured at. If 2 stages of
 378      * translation are being used then this is the intermediate
 379      * physical address that is the starting point for the second
 380      * stage of translation.
 381      */
 382     Addr faultAddr;
 383     /**
 384      * Original virtual address. If the fault was generated on the
 385      * second stage of translation then this variable stores the
 386      * virtual address used in the original stage 1 translation.
 387      */
 388     Addr OVAddr;
 389     bool write;
 390     TlbEntry::DomainType domain;
 391     uint8_t source;
 392     uint8_t srcEncoded;
 393     bool stage2;
 394     bool s1ptw;
 395     ArmFault::TranMethod tranMethod;
 396
 397   public:
 398     AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain, uint8_t _source,
 399                bool _stage2, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
 400         faultAddr(_faultAddr), write(_write), domain(_domain), source(_source),
 401         stage2(_stage2), s1ptw(false), tranMethod(_tranMethod)
 402     {}
 403
 404     void invoke(ThreadContext *tc, const StaticInstPtr &inst =
 405                 StaticInst::nullStaticInstPtr);
 406
 407     FSR getFsr(ThreadContext *tc);
 408     bool abortDisable(ThreadContext *tc);
 409     uint32_t iss() const;
 410     bool isStage2() const { return stage2; }
 411     void annotate(ArmFault::AnnotationIDs id, uint64_t val);
 412     bool isMMUFault() const;
 413 };
 414
 415 class PrefetchAbort : public AbortFault<PrefetchAbort>
 416 {
 417   public:
 418     static const MiscRegIndex FsrIndex  = MISCREG_IFSR;
 419     static const MiscRegIndex FarIndex  = MISCREG_IFAR;
 420     static const MiscRegIndex HFarIndex = MISCREG_HIFAR;
 421
 422     PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false,
 423                   ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
 424         AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess,
 425                 _source, _stage2, _tranMethod)
 426     {}
 427
 428     ExceptionClass ec(ThreadContext *tc) const;
 429     // @todo: external aborts should be routed if SCR.EA == 1
 430     bool routeToMonitor(ThreadContext *tc) const;
 431     bool routeToHyp(ThreadContext *tc) const;
 432 };
 433
 434 class DataAbort : public AbortFault<DataAbort>
 435 {
 436   public:
 437     static const MiscRegIndex FsrIndex  = MISCREG_DFSR;
 438     static const MiscRegIndex FarIndex  = MISCREG_DFAR;
 439     static const MiscRegIndex HFarIndex = MISCREG_HDFAR;
 440     bool    isv;
 441     uint8_t sas;
 442     uint8_t sse;
 443     uint8_t srt;
 444
 445     // AArch64 only
 446     bool sf;
 447     bool ar;
 448
 449     DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source,
 450               bool _stage2 = false, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
 451         AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2,
 452                               _tranMethod),
 453         isv(false), sas (0), sse(0), srt(0), sf(false), ar(false)
 454     {}
 455
 456     ExceptionClass ec(ThreadContext *tc) const;
 457     // @todo: external aborts should be routed if SCR.EA == 1
 458     bool routeToMonitor(ThreadContext *tc) const;
 459     bool routeToHyp(ThreadContext *tc) const;
 460     uint32_t iss() const;
 461     void annotate(AnnotationIDs id, uint64_t val);
 462 };
 463
 464 class VirtualDataAbort : public AbortFault<VirtualDataAbort>
 465 {
 466   public:
 467     static const MiscRegIndex FsrIndex  = MISCREG_DFSR;
 468     static const MiscRegIndex FarIndex  = MISCREG_DFAR;
 469     static const MiscRegIndex HFarIndex = MISCREG_HDFAR;
 470
 471     VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write,
 472                      uint8_t _source) :
 473         AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false)
 474     {}
 475
 476     void invoke(ThreadContext *tc, const StaticInstPtr &inst);
 477 };
 478
 479 class Interrupt : public ArmFaultVals<Interrupt>
 480 {
 481   public:
 482     bool routeToMonitor(ThreadContext *tc) const;
 483     bool routeToHyp(ThreadContext *tc) const;
 484     bool abortDisable(ThreadContext *tc);
 485 };
 486
 487 class VirtualInterrupt : public ArmFaultVals<VirtualInterrupt>
 488 {
 489   public:
 490     VirtualInterrupt();
 491 };
 492
 493 class FastInterrupt : public ArmFaultVals<FastInterrupt>
 494 {
 495   public:
 496     bool routeToMonitor(ThreadContext *tc) const;
 497     bool routeToHyp(ThreadContext *tc) const;
 498     bool abortDisable(ThreadContext *tc);
 499     bool fiqDisable(ThreadContext *tc);
 500 };
 501
 502 class VirtualFastInterrupt : public ArmFaultVals<VirtualFastInterrupt>
 503 {
 504   public:
 505     VirtualFastInterrupt();
 506 };
 507
 508 /// PC alignment fault (AArch64 only)
 509 class PCAlignmentFault : public ArmFaultVals<PCAlignmentFault>
 510 {
 511   protected:
 512     /// The unaligned value of the PC
 513     Addr faultPC;
 514   public:
 515     PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC)
 516     {}
 517     void invoke(ThreadContext *tc, const StaticInstPtr &inst =
 518                 StaticInst::nullStaticInstPtr);
 519 };
 520
 521 /// Stack pointer alignment fault (AArch64 only)
 522 class SPAlignmentFault : public ArmFaultVals<SPAlignmentFault>
 523 {
 524   public:
 525     SPAlignmentFault();
 526 };
 527
 528 /// System error (AArch64 only)
 529 class SystemError : public ArmFaultVals<SystemError>
 530 {
 531   public:
 532     SystemError();
 533     void invoke(ThreadContext *tc, const StaticInstPtr &inst =
 534                 StaticInst::nullStaticInstPtr);
 535     bool routeToMonitor(ThreadContext *tc) const;
 536     bool routeToHyp(ThreadContext *tc) const;
 537 };
 538
 539 // A fault that flushes the pipe, excluding the faulting instructions
 540 class FlushPipe : public ArmFaultVals<FlushPipe>
 541 {
 542   public:
 543     FlushPipe() {}
 544     void invoke(ThreadContext *tc, const StaticInstPtr &inst =
 545                 StaticInst::nullStaticInstPtr);
 546 };
 547
 548 // A fault that flushes the pipe, excluding the faulting instructions
 549 class ArmSev : public ArmFaultVals<ArmSev>
 550 {
 551   public:
 552     ArmSev () {}
 553     void invoke(ThreadContext *tc, const StaticInstPtr &inst =
 554                 StaticInst::nullStaticInstPtr);
 555 };
 556
 557 /// Illegal Instruction Set State fault (AArch64 only)
 558 class IllegalInstSetStateFault : public ArmFaultVals<IllegalInstSetStateFault>
 559 {
 560   public:
 561     IllegalInstSetStateFault();
 562 };
 563
 564 } // namespace ArmISA
 565
 566 #endif // __ARM_FAULTS_HH__