src/arch/arm/faults.hh

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2007-2008 The Florida State University
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Ali Saidi
  42  *          Gabe Black
  43  */
  44
  45 #ifndef __ARM_FAULTS_HH__
  46 #define __ARM_FAULTS_HH__
  47
  48 #include "arch/arm/miscregs.hh"
  49 #include "arch/arm/types.hh"
  50 #include "config/full_system.hh"
  51 #include "sim/faults.hh"
  52 #include "base/misc.hh"
  53
  54 // The design of the "name" and "vect" functions is in sim/faults.hh
  55
  56 namespace ArmISA
  57 {
  58 typedef const Addr FaultOffset;
  59
  60 class ArmFault : public FaultBase
  61 {
  62   protected:
  63     Addr getVector(ThreadContext *tc);
  64
  65   public:
  66     enum StatusEncoding
  67     {
  68         // Fault Status register encodings
  69         // ARM ARM B3.9.4
  70         AlignmentFault = 0x1,
  71         DebugEvent = 0x2,
  72         AccessFlag0 = 0x3,
  73         InstructionCacheMaintenance = 0x4,
  74         Translation0 = 0x5,
  75         AccessFlag1 = 0x6,
  76         Translation1 = 0x7,
  77         SynchronousExternalAbort0 = 0x8,
  78         Domain0 = 0x9,
  79         SynchronousExternalAbort1 = 0x8,
  80         Domain1 = 0xb,
  81         TranslationTableWalkExtAbt0 = 0xc,
  82         Permission0 = 0xd,
  83         TranslationTableWalkExtAbt1 = 0xe,
  84         Permission1 = 0xf,
  85         AsynchronousExternalAbort = 0x16,
  86         MemoryAccessAsynchronousParityError = 0x18,
  87         MemoryAccessSynchronousParityError = 0x19,
  88         TranslationTableWalkPrtyErr0 = 0x1c,
  89         TranslationTableWalkPrtyErr1 = 0x1e,
  90
  91         // not a real fault. This is a status code
  92         // to allow the translation function to inform
  93         // the memory access function not to proceed
  94         // for a Prefetch that misses in the TLB.
  95         PrefetchTLBMiss
  96     };
  97
  98     struct FaultVals
  99     {
 100         const FaultName name;
 101         const FaultOffset offset;
 102         const OperatingMode nextMode;
 103         const uint8_t armPcOffset;
 104         const uint8_t thumbPcOffset;
 105         const bool abortDisable;
 106         const bool fiqDisable;
 107         FaultStat count;
 108     };
 109
 110 #if FULL_SYSTEM
 111     void invoke(ThreadContext *tc,
 112             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 113 #endif
 114     virtual FaultStat& countStat() = 0;
 115     virtual FaultOffset offset() = 0;
 116     virtual OperatingMode nextMode() = 0;
 117     virtual uint8_t armPcOffset() = 0;
 118     virtual uint8_t thumbPcOffset() = 0;
 119     virtual bool abortDisable() = 0;
 120     virtual bool fiqDisable() = 0;
 121 };
 122
 123 template<typename T>
 124 class ArmFaultVals : public ArmFault
 125 {
 126   protected:
 127     static FaultVals vals;
 128
 129   public:
 130     FaultName name() const { return vals.name; }
 131     FaultStat & countStat() {return vals.count;}
 132     FaultOffset offset() { return vals.offset; }
 133     OperatingMode nextMode() { return vals.nextMode; }
 134     uint8_t armPcOffset() { return vals.armPcOffset; }
 135     uint8_t thumbPcOffset() { return vals.thumbPcOffset; }
 136     bool abortDisable() { return vals.abortDisable; }
 137     bool fiqDisable() { return vals.fiqDisable; }
 138 };
 139
 140 class Reset : public ArmFaultVals<Reset>
 141 #if FULL_SYSTEM
 142 {
 143   public:
 144     void invoke(ThreadContext *tc,
 145             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 146 };
 147 #else
 148 {};
 149 #endif //FULL_SYSTEM
 150
 151 class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
 152 {
 153 #if !FULL_SYSTEM
 154   protected:
 155     ExtMachInst machInst;
 156     bool unknown;
 157     const char *mnemonic;
 158     bool disabled;
 159
 160   public:
 161     UndefinedInstruction(ExtMachInst _machInst,
 162                          bool _unknown,
 163                          const char *_mnemonic = NULL,
 164                          bool _disabled = false) :
 165         machInst(_machInst), unknown(_unknown),
 166         mnemonic(_mnemonic), disabled(_disabled)
 167     {
 168     }
 169
 170     void invoke(ThreadContext *tc,
 171             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 172 #endif
 173 };
 174
 175 class SupervisorCall : public ArmFaultVals<SupervisorCall>
 176 {
 177 #if !FULL_SYSTEM
 178   protected:
 179     ExtMachInst machInst;
 180
 181   public:
 182     SupervisorCall(ExtMachInst _machInst) : machInst(_machInst)
 183     {}
 184
 185     void invoke(ThreadContext *tc,
 186             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 187 #endif
 188 };
 189
 190 template <class T>
 191 class AbortFault : public ArmFaultVals<T>
 192 {
 193   protected:
 194     Addr faultAddr;
 195     bool write;
 196     uint8_t domain;
 197     uint8_t status;
 198
 199   public:
 200     AbortFault(Addr _faultAddr, bool _write,
 201             uint8_t _domain, uint8_t _status) :
 202         faultAddr(_faultAddr), write(_write),
 203         domain(_domain), status(_status)
 204     {}
 205
 206     void invoke(ThreadContext *tc,
 207             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 208 };
 209
 210 class PrefetchAbort : public AbortFault<PrefetchAbort>
 211 {
 212   public:
 213     static const MiscRegIndex FsrIndex = MISCREG_IFSR;
 214     static const MiscRegIndex FarIndex = MISCREG_IFAR;
 215
 216     PrefetchAbort(Addr _addr, uint8_t _status) :
 217         AbortFault<PrefetchAbort>(_addr, false, 0, _status)
 218     {}
 219 };
 220
 221 class DataAbort : public AbortFault<DataAbort>
 222 {
 223   public:
 224     static const MiscRegIndex FsrIndex = MISCREG_DFSR;
 225     static const MiscRegIndex FarIndex = MISCREG_DFAR;
 226
 227     DataAbort(Addr _addr, uint8_t _domain, bool _write, uint8_t _status) :
 228         AbortFault<DataAbort>(_addr, _write, _domain, _status)
 229     {}
 230 };
 231
 232 class Interrupt : public ArmFaultVals<Interrupt> {};
 233 class FastInterrupt : public ArmFaultVals<FastInterrupt> {};
 234
 235 // A fault that flushes the pipe, excluding the faulting instructions
 236 class FlushPipe : public ArmFaultVals<FlushPipe>
 237 {
 238   public:
 239     FlushPipe() {}
 240     void invoke(ThreadContext *tc,
 241             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 242 };
 243
 244 static inline Fault genMachineCheckFault()
 245 {
 246     return new Reset();
 247 }
 248
 249 } // ArmISA namespace
 250
 251 #endif // __ARM_FAULTS_HH__