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45 #ifndef __ARM_FAULTS_HH__
46 #define __ARM_FAULTS_HH__
48 #include "arch/arm/miscregs.hh"
49 #include "arch/arm/types.hh"
50 #include "config/full_system.hh"
51 #include "sim/faults.hh"
52 #include "base/misc.hh"
54 // The design of the "name" and "vect" functions is in sim/faults.hh
58 typedef const Addr FaultOffset;
60 class ArmFault : public FaultBase
63 Addr getVector(ThreadContext *tc);
68 // Fault Status register encodings
73 InstructionCacheMaintenance = 0x4,
77 SynchronousExternalAbort0 = 0x8,
79 SynchronousExternalAbort1 = 0x8,
81 TranslationTableWalkExtAbt0 = 0xc,
83 TranslationTableWalkExtAbt1 = 0xe,
85 AsynchronousExternalAbort = 0x16,
86 MemoryAccessAsynchronousParityError = 0x18,
87 MemoryAccessSynchronousParityError = 0x19,
88 TranslationTableWalkPrtyErr0 = 0x1c,
89 TranslationTableWalkPrtyErr1 = 0x1e,
91 // not a real fault. This is a status code
92 // to allow the translation function to inform
93 // the memory access function not to proceed
94 // for a Prefetch that misses in the TLB.
100 const FaultName name;
101 const FaultOffset offset;
102 const OperatingMode nextMode;
103 const uint8_t armPcOffset;
104 const uint8_t thumbPcOffset;
105 const bool abortDisable;
106 const bool fiqDisable;
111 void invoke(ThreadContext *tc,
112 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
114 virtual FaultStat& countStat() = 0;
115 virtual FaultOffset offset() = 0;
116 virtual OperatingMode nextMode() = 0;
117 virtual uint8_t armPcOffset() = 0;
118 virtual uint8_t thumbPcOffset() = 0;
119 virtual bool abortDisable() = 0;
120 virtual bool fiqDisable() = 0;
124 class ArmFaultVals : public ArmFault
127 static FaultVals vals;
130 FaultName name() const { return vals.name; }
131 FaultStat & countStat() {return vals.count;}
132 FaultOffset offset() { return vals.offset; }
133 OperatingMode nextMode() { return vals.nextMode; }
134 uint8_t armPcOffset() { return vals.armPcOffset; }
135 uint8_t thumbPcOffset() { return vals.thumbPcOffset; }
136 bool abortDisable() { return vals.abortDisable; }
137 bool fiqDisable() { return vals.fiqDisable; }
140 class Reset : public ArmFaultVals<Reset>
144 void invoke(ThreadContext *tc,
145 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
151 class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
155 ExtMachInst machInst;
157 const char *mnemonic;
161 UndefinedInstruction(ExtMachInst _machInst,
163 const char *_mnemonic = NULL,
164 bool _disabled = false) :
165 machInst(_machInst), unknown(_unknown),
166 mnemonic(_mnemonic), disabled(_disabled)
170 void invoke(ThreadContext *tc,
171 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
175 class SupervisorCall : public ArmFaultVals<SupervisorCall>
179 ExtMachInst machInst;
182 SupervisorCall(ExtMachInst _machInst) : machInst(_machInst)
185 void invoke(ThreadContext *tc,
186 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
191 class AbortFault : public ArmFaultVals<T>
200 AbortFault(Addr _faultAddr, bool _write,
201 uint8_t _domain, uint8_t _status) :
202 faultAddr(_faultAddr), write(_write),
203 domain(_domain), status(_status)
206 void invoke(ThreadContext *tc,
207 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
210 class PrefetchAbort : public AbortFault<PrefetchAbort>
213 static const MiscRegIndex FsrIndex = MISCREG_IFSR;
214 static const MiscRegIndex FarIndex = MISCREG_IFAR;
216 PrefetchAbort(Addr _addr, uint8_t _status) :
217 AbortFault<PrefetchAbort>(_addr, false, 0, _status)
221 class DataAbort : public AbortFault<DataAbort>
224 static const MiscRegIndex FsrIndex = MISCREG_DFSR;
225 static const MiscRegIndex FarIndex = MISCREG_DFAR;
227 DataAbort(Addr _addr, uint8_t _domain, bool _write, uint8_t _status) :
228 AbortFault<DataAbort>(_addr, _write, _domain, _status)
232 class Interrupt : public ArmFaultVals<Interrupt> {};
233 class FastInterrupt : public ArmFaultVals<FastInterrupt> {};
235 // A fault that flushes the pipe, excluding the faulting instructions
236 class FlushPipe : public ArmFaultVals<FlushPipe>
240 void invoke(ThreadContext *tc,
241 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
244 static inline Fault genMachineCheckFault()
249 } // ArmISA namespace
251 #endif // __ARM_FAULTS_HH__