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15 * Copyright (c) 2007-2008 The Florida State University
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45 #ifndef __ARM_FAULTS_HH__
46 #define __ARM_FAULTS_HH__
48 #include "arch/arm/miscregs.hh"
49 #include "arch/arm/types.hh"
50 #include "config/full_system.hh"
51 #include "sim/faults.hh"
52 #include "base/misc.hh"
54 // The design of the "name" and "vect" functions is in sim/faults.hh
58 typedef const Addr FaultOffset;
60 class ArmFault : public FaultBase
63 Addr getVector(ThreadContext *tc);
68 // Fault Status register encodings
73 InstructionCacheMaintenance = 0x4,
77 SynchronousExternalAbort0 = 0x8,
79 SynchronousExternalAbort1 = 0x8,
81 TranslationTableWalkExtAbt0 = 0xc,
83 TranslationTableWalkExtAbt1 = 0xe,
85 AsynchronousExternalAbort = 0x16,
86 MemoryAccessAsynchronousParityError = 0x18,
87 MemoryAccessSynchronousParityError = 0x19,
88 TranslationTableWalkPrtyErr0 = 0x1c,
89 TranslationTableWalkPrtyErr1 = 0x1e,
91 // not a real fault. This is a status code
92 // to allow the translation function to inform
93 // the memory access function not to proceed
94 // for a Prefetch that misses in the TLB.
100 const FaultName name;
101 const FaultOffset offset;
102 const OperatingMode nextMode;
103 const uint8_t armPcOffset;
104 const uint8_t thumbPcOffset;
105 const bool abortDisable;
106 const bool fiqDisable;
111 void invoke(ThreadContext *tc);
113 virtual FaultStat& countStat() = 0;
114 virtual FaultOffset offset() = 0;
115 virtual OperatingMode nextMode() = 0;
116 virtual uint8_t armPcOffset() = 0;
117 virtual uint8_t thumbPcOffset() = 0;
118 virtual bool abortDisable() = 0;
119 virtual bool fiqDisable() = 0;
123 class ArmFaultVals : public ArmFault
126 static FaultVals vals;
129 FaultName name() const { return vals.name; }
130 FaultStat & countStat() {return vals.count;}
131 FaultOffset offset() { return vals.offset; }
132 OperatingMode nextMode() { return vals.nextMode; }
133 uint8_t armPcOffset() { return vals.armPcOffset; }
134 uint8_t thumbPcOffset() { return vals.thumbPcOffset; }
135 bool abortDisable() { return vals.abortDisable; }
136 bool fiqDisable() { return vals.fiqDisable; }
139 class Reset : public ArmFaultVals<Reset>
143 void invoke(ThreadContext *tc);
149 class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
153 ExtMachInst machInst;
155 const char *mnemonic;
159 UndefinedInstruction(ExtMachInst _machInst,
161 const char *_mnemonic = NULL,
162 bool _disabled = false) :
163 machInst(_machInst), unknown(_unknown),
164 mnemonic(_mnemonic), disabled(_disabled)
168 void invoke(ThreadContext *tc);
172 class SupervisorCall : public ArmFaultVals<SupervisorCall>
176 ExtMachInst machInst;
179 SupervisorCall(ExtMachInst _machInst) : machInst(_machInst)
182 void invoke(ThreadContext *tc);
187 class AbortFault : public ArmFaultVals<T>
196 AbortFault(Addr _faultAddr, bool _write,
197 uint8_t _domain, uint8_t _status) :
198 faultAddr(_faultAddr), write(_write),
199 domain(_domain), status(_status)
202 void invoke(ThreadContext *tc);
205 class PrefetchAbort : public AbortFault<PrefetchAbort>
208 static const MiscRegIndex FsrIndex = MISCREG_IFSR;
209 static const MiscRegIndex FarIndex = MISCREG_IFAR;
211 PrefetchAbort(Addr _addr, uint8_t _status) :
212 AbortFault<PrefetchAbort>(_addr, false, 0, _status)
216 class DataAbort : public AbortFault<DataAbort>
219 static const MiscRegIndex FsrIndex = MISCREG_DFSR;
220 static const MiscRegIndex FarIndex = MISCREG_DFAR;
222 DataAbort(Addr _addr, uint8_t _domain, bool _write, uint8_t _status) :
223 AbortFault<DataAbort>(_addr, _write, _domain, _status)
227 class Interrupt : public ArmFaultVals<Interrupt> {};
228 class FastInterrupt : public ArmFaultVals<FastInterrupt> {};
230 // A fault that flushes the pipe, excluding the faulting instructions
231 class FlushPipe : public ArmFaultVals<FlushPipe>
235 void invoke(ThreadContext *tc);
238 static inline Fault genMachineCheckFault()
243 } // ArmISA namespace
245 #endif // __ARM_FAULTS_HH__