src/arch/arm/htm.cc

   1 /*
   2  * Copyright (c) 2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #include "arch/arm/htm.hh"
  39 #include "cpu/thread_context.hh"
  40
  41 void
  42 ArmISA::HTMCheckpoint::reset()
  43 {
  44     rt = 0;
  45     nPc = 0;
  46     sp = 0;
  47     fpcr = 0;
  48     fpsr = 0;
  49     iccPmrEl1 = 0;
  50     nzcv = 0;
  51     daif = 0;
  52     tcreason = 0;
  53     x.fill(0);
  54     for (auto i = 0; i < NumVecRegs; ++i) {
  55       z[i].zero();
  56     }
  57     for (auto i = 0; i < NumVecPredRegs; ++i) {
  58       p[i].reset();
  59     }
  60     pcstateckpt = PCState();
  61
  62     BaseHTMCheckpoint::reset();
  63 }
  64
  65 void
  66 ArmISA::HTMCheckpoint::save(ThreadContext *tc)
  67 {
  68     sp = tc->readIntReg(INTREG_SPX);
  69     // below should be enabled on condition that GICV3 is enabled
  70     //tme_checkpoint->iccPmrEl1 = tc->readMiscReg(MISCREG_ICC_PMR_EL1);
  71     nzcv = tc->readMiscReg(MISCREG_NZCV);
  72     daif = tc->readMiscReg(MISCREG_DAIF);
  73     for (auto n = 0; n < NumIntArchRegs; n++) {
  74         x[n] = tc->readIntReg(n);
  75     }
  76     // TODO first detect if FP is enabled at this EL
  77     for (auto n = 0; n < NumVecRegs; n++) {
  78         RegId idx = RegId(VecRegClass, n);
  79         z[n] = tc->readVecReg(idx);
  80     }
  81     for (auto n = 0; n < NumVecPredRegs; n++) {
  82         RegId idx = RegId(VecPredRegClass, n);
  83         p[n] = tc->readVecPredReg(idx);
  84     }
  85     fpcr = tc->readMiscReg(MISCREG_FPCR);
  86     fpsr = tc->readMiscReg(MISCREG_FPSR);
  87     pcstateckpt = tc->pcState();
  88
  89     BaseHTMCheckpoint::save(tc);
  90 }
  91
  92 void
  93 ArmISA::HTMCheckpoint::restore(ThreadContext *tc, HtmFailureFaultCause cause)
  94 {
  95     tc->setIntReg(INTREG_SPX, sp);
  96     // below should be enabled on condition that GICV3 is enabled
  97     //tc->setMiscReg(MISCREG_ICC_PMR_EL1, tme_checkpoint->iccPmrEl1);
  98     tc->setMiscReg(MISCREG_NZCV, nzcv);
  99     tc->setMiscReg(MISCREG_DAIF, daif);
 100     for (auto n = 0; n < NumIntArchRegs; n++) {
 101         tc->setIntReg(n, x[n]);
 102     }
 103     // TODO first detect if FP is enabled at this EL
 104     for (auto n = 0; n < NumVecRegs; n++) {
 105         RegId idx = RegId(VecRegClass, n);
 106         tc->setVecReg(idx, z[n]);
 107     }
 108     for (auto n = 0; n < NumVecPredRegs; n++) {
 109         RegId idx = RegId(VecPredRegClass, n);
 110         tc->setVecPredReg(idx, p[n]);
 111     }
 112     tc->setMiscReg(MISCREG_FPCR, fpcr);
 113     tc->setMiscReg(MISCREG_FPSR, fpsr);
 114
 115     // this code takes the generic HTM failure reason
 116     // and prepares an Arm/TME-specific error code
 117     // which is written to a destination register
 118
 119     bool interrupt = false; // TODO get this from threadcontext
 120     bool retry = false;
 121     uint64_t error_code = 0;
 122     switch (cause) {
 123       case HtmFailureFaultCause::EXPLICIT:
 124         replaceBits(error_code, 14, 0, tcreason);
 125         replaceBits(error_code, 16, 1);
 126         retry = bits(15, tcreason);
 127         break;
 128       case HtmFailureFaultCause::MEMORY:
 129         replaceBits(error_code, 17, 1);
 130         retry = true;
 131         break;
 132       case HtmFailureFaultCause::OTHER:
 133         replaceBits(error_code, 18, 1);
 134         break;
 135       case HtmFailureFaultCause::EXCEPTION:
 136         replaceBits(error_code, 19, 1);
 137         break;
 138       case HtmFailureFaultCause::SIZE:
 139         replaceBits(error_code, 20, 1);
 140         break;
 141       case HtmFailureFaultCause::NEST:
 142         replaceBits(error_code, 21, 1);
 143         break;
 144         // case HtmFailureFaultCause_DEBUG:
 145         //     replaceBits(error_code, 22, 1);
 146         //     break;
 147       default:
 148         panic("Unknown HTM failure reason\n");
 149     }
 150     assert(!retry || !interrupt);
 151     if (retry)
 152         replaceBits(error_code, 15, 1);
 153     if (interrupt)
 154         replaceBits(error_code, 23, 1);
 155     tc->setIntReg(rt, error_code);
 156
 157     // set next PC
 158     pcstateckpt.uReset();
 159     pcstateckpt.advance();
 160     tc->pcState(pcstateckpt);
 161
 162     BaseHTMCheckpoint::restore(tc, cause);
 163 }