src/arch/arm/insts/data64.hh

   1 /*
   2  * Copyright (c) 2011-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Gabe Black
  38  */
  39 #ifndef __ARCH_ARM_INSTS_DATA64_HH__
  40 #define __ARCH_ARM_INSTS_DATA64_HH__
  41
  42 #include "arch/arm/insts/static_inst.hh"
  43 #include "base/trace.hh"
  44
  45 namespace ArmISA
  46 {
  47
  48 class DataXImmOp : public ArmStaticInst
  49 {
  50   protected:
  51     IntRegIndex dest, op1;
  52     uint64_t imm;
  53
  54     DataXImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
  55                IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) :
  56         ArmStaticInst(mnem, _machInst, __opClass),
  57         dest(_dest), op1(_op1), imm(_imm)
  58     {}
  59
  60     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
  61 };
  62
  63 class DataXImmOnlyOp : public ArmStaticInst
  64 {
  65   protected:
  66     IntRegIndex dest;
  67     uint64_t imm;
  68
  69     DataXImmOnlyOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
  70                    IntRegIndex _dest, uint64_t _imm) :
  71         ArmStaticInst(mnem, _machInst, __opClass),
  72         dest(_dest), imm(_imm)
  73     {}
  74
  75     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
  76 };
  77
  78 class DataXSRegOp : public ArmStaticInst
  79 {
  80   protected:
  81     IntRegIndex dest, op1, op2;
  82     int32_t shiftAmt;
  83     ArmShiftType shiftType;
  84
  85     DataXSRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
  86                 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
  87                 int32_t _shiftAmt, ArmShiftType _shiftType) :
  88         ArmStaticInst(mnem, _machInst, __opClass),
  89         dest(_dest), op1(_op1), op2(_op2),
  90         shiftAmt(_shiftAmt), shiftType(_shiftType)
  91     {}
  92
  93     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
  94 };
  95
  96 class DataXERegOp : public ArmStaticInst
  97 {
  98   protected:
  99     IntRegIndex dest, op1, op2;
 100     ArmExtendType extendType;
 101     int32_t shiftAmt;
 102
 103     DataXERegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 104                 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
 105                 ArmExtendType _extendType, int32_t _shiftAmt) :
 106         ArmStaticInst(mnem, _machInst, __opClass),
 107         dest(_dest), op1(_op1), op2(_op2),
 108         extendType(_extendType), shiftAmt(_shiftAmt)
 109     {}
 110
 111     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 112 };
 113
 114 class DataX1RegOp : public ArmStaticInst
 115 {
 116   protected:
 117     IntRegIndex dest, op1;
 118
 119     DataX1RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 120                 IntRegIndex _dest, IntRegIndex _op1) :
 121         ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
 122     {}
 123
 124     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 125 };
 126
 127 class DataX1RegImmOp : public ArmStaticInst
 128 {
 129   protected:
 130     IntRegIndex dest, op1;
 131     uint64_t imm;
 132
 133     DataX1RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 134                    IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) :
 135         ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1),
 136         imm(_imm)
 137     {}
 138
 139     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 140 };
 141
 142 class DataX1Reg2ImmOp : public ArmStaticInst
 143 {
 144   protected:
 145     IntRegIndex dest, op1;
 146     uint64_t imm1, imm2;
 147
 148     DataX1Reg2ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 149                     IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1,
 150                     uint64_t _imm2) :
 151         ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1),
 152         imm1(_imm1), imm2(_imm2)
 153     {}
 154
 155     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 156 };
 157
 158 class DataX2RegOp : public ArmStaticInst
 159 {
 160   protected:
 161     IntRegIndex dest, op1, op2;
 162
 163     DataX2RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 164                 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) :
 165         ArmStaticInst(mnem, _machInst, __opClass),
 166         dest(_dest), op1(_op1), op2(_op2)
 167     {}
 168
 169     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 170 };
 171
 172 class DataX2RegImmOp : public ArmStaticInst
 173 {
 174   protected:
 175     IntRegIndex dest, op1, op2;
 176     uint64_t imm;
 177
 178     DataX2RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 179                    IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
 180                    uint64_t _imm) :
 181         ArmStaticInst(mnem, _machInst, __opClass),
 182         dest(_dest), op1(_op1), op2(_op2), imm(_imm)
 183     {}
 184
 185     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 186 };
 187
 188 class DataX3RegOp : public ArmStaticInst
 189 {
 190   protected:
 191     IntRegIndex dest, op1, op2, op3;
 192
 193     DataX3RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 194                 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
 195                 IntRegIndex _op3) :
 196         ArmStaticInst(mnem, _machInst, __opClass),
 197         dest(_dest), op1(_op1), op2(_op2), op3(_op3)
 198     {}
 199
 200     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 201 };
 202
 203 class DataXCondCompImmOp : public ArmStaticInst
 204 {
 205   protected:
 206     IntRegIndex op1;
 207     uint64_t imm;
 208     ConditionCode condCode;
 209     uint8_t defCc;
 210
 211     DataXCondCompImmOp(const char *mnem, ExtMachInst _machInst,
 212                       OpClass __opClass, IntRegIndex _op1, uint64_t _imm,
 213                       ConditionCode _condCode, uint8_t _defCc) :
 214         ArmStaticInst(mnem, _machInst, __opClass),
 215         op1(_op1), imm(_imm), condCode(_condCode), defCc(_defCc)
 216     {}
 217
 218     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 219 };
 220
 221 class DataXCondCompRegOp : public ArmStaticInst
 222 {
 223   protected:
 224     IntRegIndex op1, op2;
 225     ConditionCode condCode;
 226     uint8_t defCc;
 227
 228     DataXCondCompRegOp(const char *mnem, ExtMachInst _machInst,
 229                        OpClass __opClass, IntRegIndex _op1, IntRegIndex _op2,
 230                        ConditionCode _condCode, uint8_t _defCc) :
 231         ArmStaticInst(mnem, _machInst, __opClass),
 232         op1(_op1), op2(_op2), condCode(_condCode), defCc(_defCc)
 233     {}
 234
 235     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 236 };
 237
 238 class DataXCondSelOp : public ArmStaticInst
 239 {
 240   protected:
 241     IntRegIndex dest, op1, op2;
 242     ConditionCode condCode;
 243
 244     DataXCondSelOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 245                    IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
 246                    ConditionCode _condCode) :
 247         ArmStaticInst(mnem, _machInst, __opClass),
 248         dest(_dest), op1(_op1), op2(_op2), condCode(_condCode)
 249     {}
 250
 251     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 252 };
 253
 254 }
 255
 256 #endif //__ARCH_ARM_INSTS_PREDINST_HH__