2 * Copyright (c) 2010 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Stephen Hines
43 #include "arch/arm/insts/macromem.hh"
44 #include "arch/arm/decoder.hh"
46 using namespace ArmISAInst
;
51 MacroMemOp::MacroMemOp(const char *mnem
, ExtMachInst machInst
,
52 OpClass __opClass
, IntRegIndex rn
,
53 bool index
, bool up
, bool user
, bool writeback
,
54 bool load
, uint32_t reglist
) :
55 PredMacroOp(mnem
, machInst
, __opClass
)
57 uint32_t regs
= reglist
;
58 uint32_t ones
= number_of_ones(reglist
);
59 // Remember that writeback adds a uop
60 numMicroops
= ones
+ (writeback
? 1 : 0) + 1;
61 microOps
= new StaticInstPtr
[numMicroops
];
65 addr
= (ones
<< 2) - 4;
70 StaticInstPtr
*uop
= microOps
;
74 wbUop
= new MicroAddiUop(machInst
, rn
, rn
, ones
* 4);
76 wbUop
= new MicroSubiUop(machInst
, rn
, rn
, ones
* 4);
80 // Add 0 to Rn and stick it in ureg0.
81 // This is equivalent to a move.
82 *uop
= new MicroAddiUop(machInst
, INTREG_UREG0
, rn
, 0);
84 // Write back at the start for loads. This covers the ldm exception return
85 // case where the base needs to be written in the old mode. Stores may need
86 // the original value of the base, but they don't change mode and can
87 // write back at the end like before.
88 if (load
&& writeback
) {
93 bool force_user
= user
& !bits(reglist
, 15);
94 bool exception_ret
= user
& bits(reglist
, 15);
96 for (int i
= 0; i
< ones
; i
++) {
97 // Find the next register.
98 while (!bits(regs
, reg
))
100 replaceBits(regs
, reg
, 0);
102 unsigned regIdx
= reg
;
104 regIdx
= intRegForceUser(regIdx
);
108 if (reg
== INTREG_PC
&& exception_ret
) {
109 // This must be the exception return form of ldm.
110 *++uop
= new MicroLdrRetUop(machInst
, regIdx
,
111 INTREG_UREG0
, up
, addr
);
113 *++uop
= new MicroLdrUop(machInst
, regIdx
,
114 INTREG_UREG0
, up
, addr
);
117 *++uop
= new MicroStrUop(machInst
, regIdx
, INTREG_UREG0
, up
, addr
);
126 if (!load
&& writeback
) {
130 (*uop
)->setLastMicroop();
133 MacroVFPMemOp::MacroVFPMemOp(const char *mnem
, ExtMachInst machInst
,
134 OpClass __opClass
, IntRegIndex rn
,
135 RegIndex vd
, bool single
, bool up
,
136 bool writeback
, bool load
, uint32_t offset
) :
137 PredMacroOp(mnem
, machInst
, __opClass
)
139 const int maxMicroops
= 17;
140 microOps
= new StaticInstPtr
[maxMicroops
];
143 // The lowest order bit selects fldmx (set) or fldmd (clear). These seem
144 // to be functionally identical except that fldmx is deprecated. For now
145 // we'll assume they're otherwise interchangable.
146 int count
= (single
? offset
: (offset
/ 2));
147 if (count
== 0 || count
> NumFloatArchRegs
)
148 warn_once("Bad offset field for VFP load/store multiple.\n");
150 // Force there to be at least one microop so the macroop makes sense.
153 if (count
> NumFloatArchRegs
)
154 count
= NumFloatArchRegs
;
161 for (int j
= 0; j
< count
; j
++) {
163 microOps
[i
++] = new MicroLdrFpUop(machInst
, vd
++, rn
,
166 microOps
[i
++] = new MicroLdrFpUop(machInst
, vd
++, rn
,
169 microOps
[i
++] = new MicroStrFpUop(machInst
, vd
++, rn
,
172 microOps
[i
++] = new MicroStrFpUop(machInst
, vd
++, rn
,
175 addr
+= (single
? 4 : 8);
181 new MicroAddiUop(machInst
, rn
, rn
, 4 * offset
);
184 new MicroSubiUop(machInst
, rn
, rn
, 4 * offset
);
189 assert(numMicroops
<= maxMicroops
);
190 microOps
[numMicroops
- 1]->setLastMicroop();