2 * Copyright (c) 2010-2014 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Stephen Hines
42 #ifndef __ARCH_ARM_MACROMEM_HH__
43 #define __ARCH_ARM_MACROMEM_HH__
45 #include "arch/arm/insts/pred_inst.hh"
46 #include "arch/arm/tlb.hh"
51 static inline unsigned int
52 number_of_ones(int32_t val)
55 for (int i = 0; i < 32; i++ )
64 * Base class for Memory microops
66 class MicroOp : public PredOp
69 MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass)
70 : PredOp(mnem, machInst, __opClass)
76 advancePC(PCState &pcState) const
78 if (flags[IsLastMicroop]) {
80 } else if (flags[IsMicroop]) {
88 class MicroOpX : public ArmStaticInst
91 MicroOpX(const char *mnem, ExtMachInst machInst, OpClass __opClass)
92 : ArmStaticInst(mnem, machInst, __opClass)
97 advancePC(PCState &pcState) const
99 if (flags[IsLastMicroop]) {
101 } else if (flags[IsMicroop]) {
110 * Microops for Neon loads/stores
112 class MicroNeonMemOp : public MicroOp
117 unsigned memAccessFlags;
119 MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
120 RegIndex _dest, RegIndex _ura, uint32_t _imm)
121 : MicroOp(mnem, machInst, __opClass),
122 dest(_dest), ura(_ura), imm(_imm),
123 memAccessFlags(TLB::MustBeOne)
129 * Microops for Neon load/store (de)interleaving
131 class MicroNeonMixOp : public MicroOp
137 MicroNeonMixOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
138 RegIndex _dest, RegIndex _op1, uint32_t _step)
139 : MicroOp(mnem, machInst, __opClass),
140 dest(_dest), op1(_op1), step(_step)
145 class MicroNeonMixLaneOp : public MicroNeonMixOp
150 MicroNeonMixLaneOp(const char *mnem, ExtMachInst machInst,
151 OpClass __opClass, RegIndex _dest, RegIndex _op1,
152 uint32_t _step, unsigned _lane)
153 : MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step),
160 * Microops for AArch64 NEON load/store (de)interleaving
162 class MicroNeonMixOp64 : public MicroOp
166 uint8_t eSize, dataSize, numStructElems, numRegs, step;
168 MicroNeonMixOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
169 RegIndex _dest, RegIndex _op1, uint8_t _eSize,
170 uint8_t _dataSize, uint8_t _numStructElems,
171 uint8_t _numRegs, uint8_t _step)
172 : MicroOp(mnem, machInst, __opClass), dest(_dest), op1(_op1),
173 eSize(_eSize), dataSize(_dataSize), numStructElems(_numStructElems),
174 numRegs(_numRegs), step(_step)
179 class MicroNeonMixLaneOp64 : public MicroOp
183 uint8_t eSize, dataSize, numStructElems, lane, step;
186 MicroNeonMixLaneOp64(const char *mnem, ExtMachInst machInst,
187 OpClass __opClass, RegIndex _dest, RegIndex _op1,
188 uint8_t _eSize, uint8_t _dataSize,
189 uint8_t _numStructElems, uint8_t _lane, uint8_t _step,
190 bool _replicate = false)
191 : MicroOp(mnem, machInst, __opClass), dest(_dest), op1(_op1),
192 eSize(_eSize), dataSize(_dataSize), numStructElems(_numStructElems),
193 lane(_lane), step(_step), replicate(_replicate)
199 * Base classes for microcoded AArch64 NEON memory instructions.
201 class VldMultOp64 : public PredMacroOp
204 uint8_t eSize, dataSize, numStructElems, numRegs;
207 VldMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
208 RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
209 uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs,
213 class VstMultOp64 : public PredMacroOp
216 uint8_t eSize, dataSize, numStructElems, numRegs;
219 VstMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
220 RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
221 uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs,
225 class VldSingleOp64 : public PredMacroOp
228 uint8_t eSize, dataSize, numStructElems, index;
231 VldSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
232 RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
233 uint8_t dataSize, uint8_t numStructElems, uint8_t index,
234 bool wb, bool replicate = false);
237 class VstSingleOp64 : public PredMacroOp
240 uint8_t eSize, dataSize, numStructElems, index;
243 VstSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
244 RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
245 uint8_t dataSize, uint8_t numStructElems, uint8_t index,
246 bool wb, bool replicate = false);
250 * Microops of the form
254 class MicroSetPCCPSR : public MicroOp
257 IntRegIndex ura, urb, urc;
259 MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass,
260 IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc)
261 : MicroOp(mnem, machInst, __opClass),
262 ura(_ura), urb(_urb), urc(_urc)
266 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
270 * Microops of the form IntRegA = IntRegB
272 class MicroIntMov : public MicroOp
277 MicroIntMov(const char *mnem, ExtMachInst machInst, OpClass __opClass,
278 RegIndex _ura, RegIndex _urb)
279 : MicroOp(mnem, machInst, __opClass),
284 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
288 * Microops of the form IntRegA = IntRegB op Imm
290 class MicroIntImmOp : public MicroOp
296 MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
297 RegIndex _ura, RegIndex _urb, int32_t _imm)
298 : MicroOp(mnem, machInst, __opClass),
299 ura(_ura), urb(_urb), imm(_imm)
303 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
306 class MicroIntImmXOp : public MicroOpX
312 MicroIntImmXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
313 RegIndex _ura, RegIndex _urb, int64_t _imm)
314 : MicroOpX(mnem, machInst, __opClass),
315 ura(_ura), urb(_urb), imm(_imm)
319 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
323 * Microops of the form IntRegA = IntRegB op IntRegC
325 class MicroIntOp : public MicroOp
328 RegIndex ura, urb, urc;
330 MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
331 RegIndex _ura, RegIndex _urb, RegIndex _urc)
332 : MicroOp(mnem, machInst, __opClass),
333 ura(_ura), urb(_urb), urc(_urc)
337 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
340 class MicroIntRegXOp : public MicroOp
343 RegIndex ura, urb, urc;
347 MicroIntRegXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
348 RegIndex _ura, RegIndex _urb, RegIndex _urc,
349 ArmExtendType _type, uint32_t _shiftAmt)
350 : MicroOp(mnem, machInst, __opClass),
351 ura(_ura), urb(_urb), urc(_urc),
352 type(_type), shiftAmt(_shiftAmt)
356 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
360 * Microops of the form IntRegA = IntRegB op shifted IntRegC
362 class MicroIntRegOp : public MicroOp
365 RegIndex ura, urb, urc;
367 ArmShiftType shiftType;
369 MicroIntRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
370 RegIndex _ura, RegIndex _urb, RegIndex _urc,
371 int32_t _shiftAmt, ArmShiftType _shiftType)
372 : MicroOp(mnem, machInst, __opClass),
373 ura(_ura), urb(_urb), urc(_urc),
374 shiftAmt(_shiftAmt), shiftType(_shiftType)
380 * Memory microops which use IntReg + Imm addressing
382 class MicroMemOp : public MicroIntImmOp
386 unsigned memAccessFlags;
388 MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
389 RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm)
390 : MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm),
391 up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord)
395 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
398 class MicroMemPairOp : public MicroOp
401 RegIndex dest, dest2, urb;
404 unsigned memAccessFlags;
406 MicroMemPairOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
407 RegIndex _dreg1, RegIndex _dreg2, RegIndex _base,
408 bool _up, uint8_t _imm)
409 : MicroOp(mnem, machInst, __opClass),
410 dest(_dreg1), dest2(_dreg2), urb(_base), up(_up), imm(_imm),
411 memAccessFlags(TLB::MustBeOne | TLB::AlignWord)
415 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
419 * Base class for microcoded integer memory instructions.
421 class MacroMemOp : public PredMacroOp
424 MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
425 IntRegIndex rn, bool index, bool up, bool user,
426 bool writeback, bool load, uint32_t reglist);
430 * Base class for pair load/store instructions.
432 class PairMemOp : public PredMacroOp
442 PairMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
443 uint32_t size, bool fp, bool load, bool noAlloc, bool signExt,
444 bool exclusive, bool acrel, int64_t imm, AddrMode mode,
445 IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2);
448 class BigFpMemImmOp : public PredMacroOp
451 BigFpMemImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
452 bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
455 class BigFpMemPostOp : public PredMacroOp
458 BigFpMemPostOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
459 bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
462 class BigFpMemPreOp : public PredMacroOp
465 BigFpMemPreOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
466 bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
469 class BigFpMemRegOp : public PredMacroOp
472 BigFpMemRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
473 bool load, IntRegIndex dest, IntRegIndex base,
474 IntRegIndex offset, ArmExtendType type, int64_t imm);
477 class BigFpMemLitOp : public PredMacroOp
480 BigFpMemLitOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
481 IntRegIndex dest, int64_t imm);
485 * Base classes for microcoded integer memory instructions.
487 class VldMultOp : public PredMacroOp
490 VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
491 unsigned elems, RegIndex rn, RegIndex vd, unsigned regs,
492 unsigned inc, uint32_t size, uint32_t align, RegIndex rm);
495 class VldSingleOp : public PredMacroOp
498 VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
499 bool all, unsigned elems, RegIndex rn, RegIndex vd,
500 unsigned regs, unsigned inc, uint32_t size,
501 uint32_t align, RegIndex rm, unsigned lane);
505 * Base class for microcoded integer memory instructions.
507 class VstMultOp : public PredMacroOp
510 VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
511 unsigned width, RegIndex rn, RegIndex vd, unsigned regs,
512 unsigned inc, uint32_t size, uint32_t align, RegIndex rm);
515 class VstSingleOp : public PredMacroOp
518 VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
519 bool all, unsigned elems, RegIndex rn, RegIndex vd,
520 unsigned regs, unsigned inc, uint32_t size,
521 uint32_t align, RegIndex rm, unsigned lane);
525 * Base class for microcoded floating point memory instructions.
527 class MacroVFPMemOp : public PredMacroOp
530 MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
531 IntRegIndex rn, RegIndex vd, bool single, bool up,
532 bool writeback, bool load, uint32_t offset);
537 #endif //__ARCH_ARM_INSTS_MACROMEM_HH__