src/arch/arm/insts/macromem.hh

   1 /*
   2  * Copyright (c) 2010-2014 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2007-2008 The Florida State University
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __ARCH_ARM_MACROMEM_HH__
  42 #define __ARCH_ARM_MACROMEM_HH__
  43
  44 #include "arch/arm/insts/pred_inst.hh"
  45 #include "arch/arm/tlb.hh"
  46
  47 namespace ArmISA
  48 {
  49
  50 static inline unsigned int
  51 number_of_ones(int32_t val)
  52 {
  53     uint32_t ones = 0;
  54     for (int i = 0; i < 32; i++ )
  55     {
  56         if ( val & (1<<i) )
  57             ones++;
  58     }
  59     return ones;
  60 }
  61
  62 /**
  63  * Base class for Memory microops
  64  */
  65 class MicroOp : public PredOp
  66 {
  67   protected:
  68     MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass)
  69             : PredOp(mnem, machInst, __opClass)
  70     {
  71     }
  72
  73   public:
  74     void
  75     advancePC(PCState &pcState) const override
  76     {
  77         if (flags[IsLastMicroop]) {
  78             pcState.uEnd();
  79         } else if (flags[IsMicroop]) {
  80             pcState.uAdvance();
  81         } else {
  82             pcState.advance();
  83         }
  84     }
  85 };
  86
  87 class MicroOpX : public ArmStaticInst
  88 {
  89   protected:
  90     MicroOpX(const char *mnem, ExtMachInst machInst, OpClass __opClass)
  91             : ArmStaticInst(mnem, machInst, __opClass)
  92     {}
  93
  94   public:
  95     void
  96     advancePC(PCState &pcState) const override
  97     {
  98         if (flags[IsLastMicroop]) {
  99             pcState.uEnd();
 100         } else if (flags[IsMicroop]) {
 101             pcState.uAdvance();
 102         } else {
 103             pcState.advance();
 104         }
 105     }
 106 };
 107
 108 /**
 109  * Microops for Neon loads/stores
 110  */
 111 class MicroNeonMemOp : public MicroOp
 112 {
 113   protected:
 114     RegIndex dest, ura;
 115     uint32_t imm;
 116     unsigned memAccessFlags;
 117
 118     MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 119                    RegIndex _dest, RegIndex _ura, uint32_t _imm)
 120             : MicroOp(mnem, machInst, __opClass),
 121               dest(_dest), ura(_ura), imm(_imm),
 122               memAccessFlags(TLB::MustBeOne)
 123     {
 124     }
 125 };
 126
 127 /**
 128  * Microops for Neon load/store (de)interleaving
 129  */
 130 class MicroNeonMixOp : public MicroOp
 131 {
 132   protected:
 133     RegIndex dest, op1;
 134     uint32_t step;
 135
 136     MicroNeonMixOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 137                    RegIndex _dest, RegIndex _op1, uint32_t _step)
 138             : MicroOp(mnem, machInst, __opClass),
 139               dest(_dest), op1(_op1), step(_step)
 140     {
 141     }
 142 };
 143
 144 class MicroNeonMixLaneOp : public MicroNeonMixOp
 145 {
 146   protected:
 147     unsigned lane;
 148
 149     MicroNeonMixLaneOp(const char *mnem, ExtMachInst machInst,
 150                        OpClass __opClass, RegIndex _dest, RegIndex _op1,
 151                        uint32_t _step, unsigned _lane)
 152             : MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step),
 153               lane(_lane)
 154     {
 155     }
 156 };
 157
 158 /**
 159  * Microops for AArch64 NEON load/store (de)interleaving
 160  */
 161 class MicroNeonMixOp64 : public MicroOp
 162 {
 163   protected:
 164     RegIndex dest, op1;
 165     uint8_t eSize, dataSize, numStructElems, numRegs, step;
 166
 167     MicroNeonMixOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 168                      RegIndex _dest, RegIndex _op1, uint8_t _eSize,
 169                      uint8_t _dataSize, uint8_t _numStructElems,
 170                      uint8_t _numRegs, uint8_t _step)
 171         : MicroOp(mnem, machInst, __opClass), dest(_dest), op1(_op1),
 172           eSize(_eSize), dataSize(_dataSize), numStructElems(_numStructElems),
 173           numRegs(_numRegs), step(_step)
 174     {
 175     }
 176 };
 177
 178 class MicroNeonMixLaneOp64 : public MicroOp
 179 {
 180   protected:
 181     RegIndex dest, op1;
 182     uint8_t eSize, dataSize, numStructElems, lane, step;
 183     bool replicate;
 184
 185     MicroNeonMixLaneOp64(const char *mnem, ExtMachInst machInst,
 186                          OpClass __opClass, RegIndex _dest, RegIndex _op1,
 187                          uint8_t _eSize, uint8_t _dataSize,
 188                          uint8_t _numStructElems, uint8_t _lane, uint8_t _step,
 189                          bool _replicate = false)
 190         : MicroOp(mnem, machInst, __opClass), dest(_dest), op1(_op1),
 191           eSize(_eSize), dataSize(_dataSize), numStructElems(_numStructElems),
 192           lane(_lane), step(_step), replicate(_replicate)
 193     {
 194     }
 195 };
 196
 197 /**
 198  * Base classes for microcoded AArch64 NEON memory instructions.
 199  */
 200 class VldMultOp64 : public PredMacroOp
 201 {
 202   protected:
 203     uint8_t eSize, dataSize, numStructElems, numRegs;
 204     bool wb;
 205
 206     VldMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 207                 RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
 208                 uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs,
 209                 bool wb);
 210 };
 211
 212 class VstMultOp64 : public PredMacroOp
 213 {
 214   protected:
 215     uint8_t eSize, dataSize, numStructElems, numRegs;
 216     bool wb;
 217
 218     VstMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 219                 RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
 220                 uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs,
 221                 bool wb);
 222 };
 223
 224 class VldSingleOp64 : public PredMacroOp
 225 {
 226   protected:
 227     uint8_t eSize, dataSize, numStructElems, index;
 228     bool wb, replicate;
 229
 230     VldSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 231                   RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
 232                   uint8_t dataSize, uint8_t numStructElems, uint8_t index,
 233                   bool wb, bool replicate = false);
 234 };
 235
 236 class VstSingleOp64 : public PredMacroOp
 237 {
 238   protected:
 239     uint8_t eSize, dataSize, numStructElems, index;
 240     bool wb, replicate;
 241
 242     VstSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 243                   RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
 244                   uint8_t dataSize, uint8_t numStructElems, uint8_t index,
 245                   bool wb, bool replicate = false);
 246 };
 247
 248 /**
 249  * Microops of the form
 250  * PC   = IntRegA
 251  * CPSR = IntRegB
 252  */
 253 class MicroSetPCCPSR : public MicroOp
 254 {
 255     protected:
 256     IntRegIndex ura, urb, urc;
 257
 258     MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 259                    IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc)
 260         : MicroOp(mnem, machInst, __opClass),
 261           ura(_ura), urb(_urb), urc(_urc)
 262     {
 263     }
 264
 265     std::string generateDisassembly(
 266             Addr pc, const SymbolTable *symtab) const override;
 267 };
 268
 269 /**
 270  * Microops of the form IntRegA = IntRegB
 271  */
 272 class MicroIntMov : public MicroOp
 273 {
 274   protected:
 275     RegIndex ura, urb;
 276
 277     MicroIntMov(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 278                RegIndex _ura, RegIndex _urb)
 279             : MicroOp(mnem, machInst, __opClass),
 280               ura(_ura), urb(_urb)
 281     {
 282     }
 283
 284     std::string generateDisassembly(
 285             Addr pc, const SymbolTable *symtab) const override;
 286 };
 287
 288 /**
 289  * Microops of the form IntRegA = IntRegB op Imm
 290  */
 291 class MicroIntImmOp : public MicroOp
 292 {
 293   protected:
 294     RegIndex ura, urb;
 295     int32_t imm;
 296
 297     MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 298                   RegIndex _ura, RegIndex _urb, int32_t _imm)
 299             : MicroOp(mnem, machInst, __opClass),
 300               ura(_ura), urb(_urb), imm(_imm)
 301     {
 302     }
 303
 304     std::string generateDisassembly(
 305             Addr pc, const SymbolTable *symtab) const override;
 306 };
 307
 308 class MicroIntImmXOp : public MicroOpX
 309 {
 310   protected:
 311     RegIndex ura, urb;
 312     int64_t imm;
 313
 314     MicroIntImmXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 315                    RegIndex _ura, RegIndex _urb, int64_t _imm)
 316             : MicroOpX(mnem, machInst, __opClass),
 317               ura(_ura), urb(_urb), imm(_imm)
 318     {
 319     }
 320
 321     std::string generateDisassembly(
 322             Addr pc, const SymbolTable *symtab) const override;
 323 };
 324
 325 /**
 326  * Microops of the form IntRegA = IntRegB op IntRegC
 327  */
 328 class MicroIntOp : public MicroOp
 329 {
 330   protected:
 331     RegIndex ura, urb, urc;
 332
 333     MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 334                RegIndex _ura, RegIndex _urb, RegIndex _urc)
 335             : MicroOp(mnem, machInst, __opClass),
 336               ura(_ura), urb(_urb), urc(_urc)
 337     {
 338     }
 339
 340     std::string generateDisassembly(
 341             Addr pc, const SymbolTable *symtab) const override;
 342 };
 343
 344 class MicroIntRegXOp : public MicroOp
 345 {
 346   protected:
 347     RegIndex ura, urb, urc;
 348     ArmExtendType type;
 349     uint32_t shiftAmt;
 350
 351     MicroIntRegXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 352                    RegIndex _ura, RegIndex _urb, RegIndex _urc,
 353                    ArmExtendType _type, uint32_t _shiftAmt)
 354             : MicroOp(mnem, machInst, __opClass),
 355               ura(_ura), urb(_urb), urc(_urc),
 356               type(_type), shiftAmt(_shiftAmt)
 357     {
 358     }
 359
 360     std::string generateDisassembly(
 361             Addr pc, const SymbolTable *symtab) const override;
 362 };
 363
 364 /**
 365  * Microops of the form IntRegA = IntRegB op shifted IntRegC
 366  */
 367 class MicroIntRegOp : public MicroOp
 368 {
 369   protected:
 370     RegIndex ura, urb, urc;
 371     int32_t shiftAmt;
 372     ArmShiftType shiftType;
 373
 374     MicroIntRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 375                RegIndex _ura, RegIndex _urb, RegIndex _urc,
 376                int32_t _shiftAmt, ArmShiftType _shiftType)
 377             : MicroOp(mnem, machInst, __opClass),
 378               ura(_ura), urb(_urb), urc(_urc),
 379               shiftAmt(_shiftAmt), shiftType(_shiftType)
 380     {
 381     }
 382 };
 383
 384 /**
 385  * Memory microops which use IntReg + Imm addressing
 386  */
 387 class MicroMemOp : public MicroIntImmOp
 388 {
 389   protected:
 390     bool up;
 391     unsigned memAccessFlags;
 392
 393     MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 394                RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm)
 395             : MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm),
 396               up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord)
 397     {
 398     }
 399
 400     std::string generateDisassembly(
 401             Addr pc, const SymbolTable *symtab) const override;
 402 };
 403
 404 class MicroMemPairOp : public MicroOp
 405 {
 406   protected:
 407     RegIndex dest, dest2, urb;
 408     bool up;
 409     int32_t imm;
 410     unsigned memAccessFlags;
 411
 412     MicroMemPairOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 413             RegIndex _dreg1, RegIndex _dreg2, RegIndex _base,
 414             bool _up, uint8_t _imm)
 415         : MicroOp(mnem, machInst, __opClass),
 416         dest(_dreg1), dest2(_dreg2), urb(_base), up(_up), imm(_imm),
 417         memAccessFlags(TLB::MustBeOne | TLB::AlignWord)
 418     {
 419     }
 420
 421     std::string generateDisassembly(
 422             Addr pc, const SymbolTable *symtab) const override;
 423 };
 424
 425 /**
 426  * Base class for microcoded integer memory instructions.
 427  */
 428 class MacroMemOp : public PredMacroOp
 429 {
 430   protected:
 431     MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 432                IntRegIndex rn, bool index, bool up, bool user,
 433                bool writeback, bool load, uint32_t reglist);
 434 };
 435
 436 /**
 437  * Base class for pair load/store instructions.
 438  */
 439 class PairMemOp : public PredMacroOp
 440 {
 441   public:
 442     enum AddrMode {
 443         AddrMd_Offset,
 444         AddrMd_PreIndex,
 445         AddrMd_PostIndex
 446     };
 447
 448   protected:
 449     PairMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 450               uint32_t size, bool fp, bool load, bool noAlloc, bool signExt,
 451               bool exclusive, bool acrel, int64_t imm, AddrMode mode,
 452               IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2);
 453 };
 454
 455 class BigFpMemImmOp : public PredMacroOp
 456 {
 457   protected:
 458     BigFpMemImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 459                   bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
 460 };
 461
 462 class BigFpMemPostOp : public PredMacroOp
 463 {
 464   protected:
 465     BigFpMemPostOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 466                    bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
 467 };
 468
 469 class BigFpMemPreOp : public PredMacroOp
 470 {
 471   protected:
 472     BigFpMemPreOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 473                   bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
 474 };
 475
 476 class BigFpMemRegOp : public PredMacroOp
 477 {
 478   protected:
 479     BigFpMemRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 480                   bool load, IntRegIndex dest, IntRegIndex base,
 481                   IntRegIndex offset, ArmExtendType type, int64_t imm);
 482 };
 483
 484 class BigFpMemLitOp : public PredMacroOp
 485 {
 486   protected:
 487     BigFpMemLitOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 488                   IntRegIndex dest, int64_t imm);
 489 };
 490
 491 /**
 492  * Base classes for microcoded integer memory instructions.
 493  */
 494 class VldMultOp : public PredMacroOp
 495 {
 496   protected:
 497     VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 498               unsigned elems, RegIndex rn, RegIndex vd, unsigned regs,
 499               unsigned inc, uint32_t size, uint32_t align, RegIndex rm);
 500 };
 501
 502 class VldSingleOp : public PredMacroOp
 503 {
 504   protected:
 505     VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 506                 bool all, unsigned elems, RegIndex rn, RegIndex vd,
 507                 unsigned regs, unsigned inc, uint32_t size,
 508                 uint32_t align, RegIndex rm, unsigned lane);
 509 };
 510
 511 /**
 512  * Base class for microcoded integer memory instructions.
 513  */
 514 class VstMultOp : public PredMacroOp
 515 {
 516   protected:
 517     VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 518               unsigned width, RegIndex rn, RegIndex vd, unsigned regs,
 519               unsigned inc, uint32_t size, uint32_t align, RegIndex rm);
 520 };
 521
 522 class VstSingleOp : public PredMacroOp
 523 {
 524   protected:
 525     VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 526                 bool all, unsigned elems, RegIndex rn, RegIndex vd,
 527                 unsigned regs, unsigned inc, uint32_t size,
 528                 uint32_t align, RegIndex rm, unsigned lane);
 529 };
 530
 531 /**
 532  * Base class for microcoded floating point memory instructions.
 533  */
 534 class MacroVFPMemOp : public PredMacroOp
 535 {
 536   protected:
 537     MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 538                   IntRegIndex rn, RegIndex vd, bool single, bool up,
 539                   bool writeback, bool load, uint32_t offset);
 540 };
 541
 542 }
 543
 544 #endif //__ARCH_ARM_INSTS_MACROMEM_HH__