2 * Copyright (c) 2010 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Stephen Hines
42 #ifndef __ARCH_ARM_MEM_HH__
43 #define __ARCH_ARM_MEM_HH__
45 #include "arch/arm/insts/pred_inst.hh"
50 class Swap : public PredOp
57 Swap(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
58 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _base)
59 : PredOp(mnem, _machInst, __opClass),
60 dest(_dest), op1(_op1), base(_base)
63 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
66 class MightBeMicro : public PredOp
69 MightBeMicro(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
70 : PredOp(mnem, _machInst, __opClass)
74 advancePC(PCState &pcState) const
76 if (flags[IsLastMicroop]) {
78 } else if (flags[IsMicroop]) {
86 // The address is a base register plus an immediate.
87 class RfeOp : public MightBeMicro
100 IntRegIndex ura, urb, urc;
101 static const unsigned numMicroops = 3;
105 RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
106 IntRegIndex _base, AddrMode _mode, bool _wb)
107 : MightBeMicro(mnem, _machInst, __opClass),
108 base(_base), mode(_mode), wb(_wb),
109 ura(INTREG_UREG0), urb(INTREG_UREG1),
121 fetchMicroop(MicroPC microPC) const
123 assert(uops != NULL && microPC < numMicroops);
124 return uops[microPC];
127 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
130 // The address is a base register plus an immediate.
131 class SrsOp : public MightBeMicro
144 static const unsigned numMicroops = 2;
148 SrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
149 uint32_t _regMode, AddrMode _mode, bool _wb)
150 : MightBeMicro(mnem, _machInst, __opClass),
151 regMode(_regMode), mode(_mode), wb(_wb), uops(NULL)
161 fetchMicroop(MicroPC microPC) const
163 assert(uops != NULL && microPC < numMicroops);
164 return uops[microPC];
167 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
170 class Memory : public MightBeMicro
184 static const unsigned numMicroops = 3;
188 Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
189 IntRegIndex _dest, IntRegIndex _base, bool _add)
190 : MightBeMicro(mnem, _machInst, __opClass),
191 dest(_dest), base(_base), add(_add), uops(NULL)
201 fetchMicroop(MicroPC microPC) const
203 assert(uops != NULL && microPC < numMicroops);
204 return uops[microPC];
208 printOffset(std::ostream &os) const
212 printDest(std::ostream &os) const
217 void printInst(std::ostream &os, AddrMode addrMode) const;
220 // The address is a base register plus an immediate.
221 class MemoryImm : public Memory
226 MemoryImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
227 IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
228 : Memory(mnem, _machInst, __opClass, _dest, _base, _add), imm(_imm)
232 printOffset(std::ostream &os) const
237 ccprintf(os, "#%d", pImm);
241 class MemoryExImm : public MemoryImm
246 MemoryExImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
247 IntRegIndex _result, IntRegIndex _dest, IntRegIndex _base,
248 bool _add, int32_t _imm)
249 : MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm),
254 printDest(std::ostream &os) const
256 printReg(os, result);
258 MemoryImm::printDest(os);
262 // The address is a base register plus an immediate.
263 class MemoryDImm : public MemoryImm
268 MemoryDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
269 IntRegIndex _dest, IntRegIndex _dest2,
270 IntRegIndex _base, bool _add, int32_t _imm)
271 : MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm),
276 printDest(std::ostream &os) const
278 MemoryImm::printDest(os);
284 class MemoryExDImm : public MemoryDImm
289 MemoryExDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
290 IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
291 IntRegIndex _base, bool _add, int32_t _imm)
292 : MemoryDImm(mnem, _machInst, __opClass, _dest, _dest2,
293 _base, _add, _imm), result(_result)
297 printDest(std::ostream &os) const
299 printReg(os, result);
301 MemoryDImm::printDest(os);
305 // The address is a shifted register plus an immediate
306 class MemoryReg : public Memory
310 ArmShiftType shiftType;
313 MemoryReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
314 IntRegIndex _dest, IntRegIndex _base, bool _add,
315 int32_t _shiftAmt, ArmShiftType _shiftType,
317 : Memory(mnem, _machInst, __opClass, _dest, _base, _add),
318 shiftAmt(_shiftAmt), shiftType(_shiftType), index(_index)
321 void printOffset(std::ostream &os) const;
324 class MemoryDReg : public MemoryReg
329 MemoryDReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
330 IntRegIndex _dest, IntRegIndex _dest2,
331 IntRegIndex _base, bool _add,
332 int32_t _shiftAmt, ArmShiftType _shiftType,
334 : MemoryReg(mnem, _machInst, __opClass, _dest, _base, _add,
335 _shiftAmt, _shiftType, _index),
340 printDest(std::ostream &os) const
342 MemoryReg::printDest(os);
349 class MemoryOffset : public Base
352 MemoryOffset(const char *mnem, ExtMachInst _machInst,
353 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
354 bool _add, int32_t _imm)
355 : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
358 MemoryOffset(const char *mnem, ExtMachInst _machInst,
359 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
360 bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
362 : Base(mnem, _machInst, __opClass, _dest, _base, _add,
363 _shiftAmt, _shiftType, _index)
366 MemoryOffset(const char *mnem, ExtMachInst _machInst,
367 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
368 IntRegIndex _base, bool _add, int32_t _imm)
369 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
372 MemoryOffset(const char *mnem, ExtMachInst _machInst,
373 OpClass __opClass, IntRegIndex _result,
374 IntRegIndex _dest, IntRegIndex _dest2,
375 IntRegIndex _base, bool _add, int32_t _imm)
376 : Base(mnem, _machInst, __opClass, _result,
377 _dest, _dest2, _base, _add, _imm)
380 MemoryOffset(const char *mnem, ExtMachInst _machInst,
381 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
382 IntRegIndex _base, bool _add,
383 int32_t _shiftAmt, ArmShiftType _shiftType,
385 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
386 _shiftAmt, _shiftType, _index)
390 generateDisassembly(Addr pc, const SymbolTable *symtab) const
392 std::stringstream ss;
393 this->printInst(ss, Memory::AddrMd_Offset);
399 class MemoryPreIndex : public Base
402 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
403 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
404 bool _add, int32_t _imm)
405 : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
408 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
409 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
410 bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
412 : Base(mnem, _machInst, __opClass, _dest, _base, _add,
413 _shiftAmt, _shiftType, _index)
416 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
417 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
418 IntRegIndex _base, bool _add, int32_t _imm)
419 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
422 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
423 OpClass __opClass, IntRegIndex _result,
424 IntRegIndex _dest, IntRegIndex _dest2,
425 IntRegIndex _base, bool _add, int32_t _imm)
426 : Base(mnem, _machInst, __opClass, _result,
427 _dest, _dest2, _base, _add, _imm)
430 MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
431 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
432 IntRegIndex _base, bool _add,
433 int32_t _shiftAmt, ArmShiftType _shiftType,
435 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
436 _shiftAmt, _shiftType, _index)
440 generateDisassembly(Addr pc, const SymbolTable *symtab) const
442 std::stringstream ss;
443 this->printInst(ss, Memory::AddrMd_PreIndex);
449 class MemoryPostIndex : public Base
452 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
453 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
454 bool _add, int32_t _imm)
455 : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
458 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
459 OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
460 bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
462 : Base(mnem, _machInst, __opClass, _dest, _base, _add,
463 _shiftAmt, _shiftType, _index)
466 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
467 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
468 IntRegIndex _base, bool _add, int32_t _imm)
469 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
472 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
473 OpClass __opClass, IntRegIndex _result,
474 IntRegIndex _dest, IntRegIndex _dest2,
475 IntRegIndex _base, bool _add, int32_t _imm)
476 : Base(mnem, _machInst, __opClass, _result,
477 _dest, _dest2, _base, _add, _imm)
480 MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
481 OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
482 IntRegIndex _base, bool _add,
483 int32_t _shiftAmt, ArmShiftType _shiftType,
485 : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
486 _shiftAmt, _shiftType, _index)
490 generateDisassembly(Addr pc, const SymbolTable *symtab) const
492 std::stringstream ss;
493 this->printInst(ss, Memory::AddrMd_PostIndex);
499 #endif //__ARCH_ARM_INSTS_MEM_HH__