6320bb6da53680f36d037b1748ee74fc5150d57d
2 * Copyright (c) 2010 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are
17 * met: redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer;
19 * redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution;
22 * neither the name of the copyright holders nor the names of its
23 * contributors may be used to endorse or promote products derived from
24 * this software without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 #include "arch/arm/insts/misc.hh"
42 #include "cpu/reg_class.hh"
45 MrsOp::generateDisassembly(Addr pc
, const SymbolTable
*symtab
) const
51 bool foundPsr
= false;
52 for (unsigned i
= 0; i
< numSrcRegs(); i
++) {
53 RegIndex idx
= srcRegIdx(i
);
55 if (regIdxToClass(idx
, &rel_idx
) != MiscRegClass
) {
58 if (rel_idx
== MISCREG_CPSR
) {
63 if (rel_idx
== MISCREG_SPSR
) {
76 MsrBase::printMsrBase(std::ostream
&os
) const
80 bool foundPsr
= false;
81 for (unsigned i
= 0; i
< numDestRegs(); i
++) {
82 int idx
= destRegIdx(i
);
83 if (idx
< Misc_Reg_Base
) {
87 if (idx
== MISCREG_CPSR
) {
92 if (idx
== MISCREG_SPSR
) {
93 if (bits(byteMask
, 1, 0)) {
107 if (bits(byteMask
, 3)) {
114 if (bits(byteMask
, 2)) {
121 if (bits(byteMask
, 1)) {
124 if (bits(byteMask
, 0)) {
130 MsrImmOp::generateDisassembly(Addr pc
, const SymbolTable
*symtab
) const
132 std::stringstream ss
;
134 ccprintf(ss
, ", #%#x", imm
);
139 MsrRegOp::generateDisassembly(Addr pc
, const SymbolTable
*symtab
) const
141 std::stringstream ss
;
149 ImmOp::generateDisassembly(Addr pc
, const SymbolTable
*symtab
) const
151 std::stringstream ss
;
153 ccprintf(ss
, "#%d", imm
);
158 RegImmOp::generateDisassembly(Addr pc
, const SymbolTable
*symtab
) const
160 std::stringstream ss
;
163 ccprintf(ss
, ", #%d", imm
);
168 RegRegOp::generateDisassembly(Addr pc
, const SymbolTable
*symtab
) const
170 std::stringstream ss
;
179 RegRegRegImmOp::generateDisassembly(Addr pc
, const SymbolTable
*symtab
) const
181 std::stringstream ss
;
188 ccprintf(ss
, ", #%d", imm
);
193 RegRegRegRegOp::generateDisassembly(Addr pc
, const SymbolTable
*symtab
) const
195 std::stringstream ss
;
208 RegRegRegOp::generateDisassembly(Addr pc
, const SymbolTable
*symtab
) const
210 std::stringstream ss
;
221 RegRegImmOp::generateDisassembly(Addr pc
, const SymbolTable
*symtab
) const
223 std::stringstream ss
;
228 ccprintf(ss
, ", #%d", imm
);
233 RegRegImmImmOp::generateDisassembly(Addr pc
, const SymbolTable
*symtab
) const
235 std::stringstream ss
;
240 ccprintf(ss
, ", #%d, #%d", imm1
, imm2
);
245 RegImmRegOp::generateDisassembly(Addr pc
, const SymbolTable
*symtab
) const
247 std::stringstream ss
;
250 ccprintf(ss
, ", #%d, ", imm
);
256 RegImmRegShiftOp::generateDisassembly(Addr pc
, const SymbolTable
*symtab
) const
258 std::stringstream ss
;
261 ccprintf(ss
, ", #%d, ", imm
);
262 printShiftOperand(ss
, op1
, true, shiftAmt
, INTREG_ZERO
, shiftType
);
268 UnknownOp::generateDisassembly(Addr pc
, const SymbolTable
*symtab
) const
270 return csprintf("%-10s (inst %#08x)", "unknown", machInst
);